Impact of Single-Event Upsets in Deep-Submicron Silicon Technology

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 117-120 ◽  
Author(s):  
Robert Baumann
Keyword(s):  
Soft Errors ◽  
Deep Submicron ◽  
Soft Error ◽  
Mitigation Strategies ◽  
Single Event ◽  
Radiation Mechanisms ◽  
Silicon Technology ◽  
Single Event Upsets ◽  
Radiation Induced ◽  
Considerable Concern

AbstractThe once-ephemeral soft error phenomenon has recently caused considerable concern for manufacturers of advanced silicon technology. Soft errors, if unchecked, now have the potential for inducing a higher failure rate than all of the other reliability-failure mechanisms combined. This article briefly reviews the three dominant radiation mechanisms responsible for soft errors in terrestrial applications and how soft errors are generated by the collection of radiation-induced charge. Scaling trends in the soft error sensitivity of various memory and logic components are presented, along with a consideration of which applications are most likely to require intervention. Some of the mitigation strategies that can be employed to reduce the soft error rate in these devices are also discussed.

SOFT ERRORS IN COMMERCIAL INTEGRATED CIRCUITS

2004 ◽  
Vol 14 (02) ◽  
pp. 299-309 ◽  
Author(s):  
R. C. BAUMANN
Keyword(s):  
Integrated Circuits ◽  
Physical Mechanism ◽  
High Reliability ◽  
Soft Errors ◽  
Soft Error ◽  
Radiation Mechanisms ◽  
Technology Scaling ◽  
The Impact ◽  
Reliability Systems ◽  
Considerable Concern

The once-ephemeral soft error has recently caused considerable concern for manufacturers of advanced silicon technology as this phenomenon now has the potential for inducing the highest failure rate of all other reliability mechanisms combined. We briefly review the three radiation mechanisms responsible for causing soft errors in commercial electronics and the basic physical mechanism by which ionizing radiation can produce a soft error. We then focus on the soft error sensitivity trends in commercial DRAM, SRAM, and peripheral logic devices as a function of technology scaling and discuss some of the solutions used for mitigating the impact of soft errors in high reliability systems.

scholarly journals Study of single event upsets (SEUS) a survey and analysis

2021 ◽  
Author(s):  
Sheldon Mark Foulds
Keyword(s):  
Error Control ◽  
Hamming Code ◽  
Single Event ◽  
Electronic Circuits ◽  
Error Control Coding ◽  
Computing Systems ◽  
Single Event Upsets ◽  
Triple Modular Redundancy ◽  
Radiation Induced ◽  
Modular Redundancy

Over the last few years evolution in electronics technology has led to the shrinkage of electronic circuits. While this has led to the emergence of more powerful computing systems it has also caused a dramatic increase in the occurrence of soft errors and a steady climb in failure in time (FIT) rates. This problem is most prevalent in FPGA based systems which are highly susceptible to radiation induced errors. Depending upon the severity of the problem a number of methods exist to counter these effects including Triple Modular Redundancy (TMR), Error Control Coding (ECC), scrubbing systems etc. The following project presents a simulation of an FPGA based system that employs one of the popular error control code techniques called the Hamming Code. A resulting analysis shows that Hamming Code is able to mitigate the effects of single event upsets (SEUs) but suffers due to a number of limitations.

Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations

2014 ◽  
Vol 24 (01) ◽  
pp. 1550007 ◽  
Author(s):  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Mahdi Fazeli
Keyword(s):  
Propagation Delay ◽  
Soft Error ◽  
The Other ◽  
Design Parameters ◽  
Single Event ◽  
Temperature Variations ◽  
Single Event Upsets ◽  
Radiation Hardened ◽  
Simulation Results ◽  
Power Delay Product

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

Detection and repair of radiation induced single event upsets in an FPGA-based readout for TES bolometer arrays

2010 ◽  
Author(s):  
Graeme Smecher ◽  
François Aubin ◽  
Oleg Djazovski ◽  
Matt Dobbs ◽  
Gordon Faulkner ◽  
...  
Keyword(s):  
Single Event ◽  
Tes Bolometer ◽  
Single Event Upsets ◽  
Radiation Induced ◽  
Bolometer Arrays

SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

2014 ◽  
Vol 23 (06) ◽  
pp. 1450081 ◽  
Author(s):  
REZA OMIDI GOSHEBLAGH ◽  
KARIM MOHAMMADI
Keyword(s):  
Field Programmable Gate Array ◽  
Fault Injection ◽  
Soft Error ◽  
Space Systems ◽  
Single Event ◽  
Single Event Upsets ◽  
Average Area ◽  
Error Mitigation ◽  
Field Programmable ◽  
Mitigation Techniques

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

scholarly journals Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 322 ◽  
Author(s):  
Luis Aranda ◽  
Pedro Reviriego ◽  
Juan Maestro
Keyword(s):  
Image Processing ◽  
Single Event ◽  
Image Processing Algorithm ◽  
Memory Errors ◽  
Space Applications ◽  
Single Event Upsets ◽  
Error Mitigation ◽  
Speed Up ◽  
Radiation Induced ◽  
Novel Method

Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be vulnerable to configuration memory errors caused by single event upsets (SEUs). In those systems, the captured image is streamed pixel by pixel from the camera to the FPGA. Certain local operations such as median or rank filters need to process the image locally instead of pixel by pixel, so some particular pixel caching structures such as line-buffer-based pipelines can be used to accelerate the filtering process. However, an SRAM-based FPGA implementation of these pipelines may have malfunctions due to the mentioned configuration memory errors, so an error mitigation technique is required. In this paper, a novel method to protect line-buffer-based pipelines against SRAM-based FPGA configuration memory errors is presented. Experimental results show that, using our protection technique, considerable savings in terms of FPGA resources can be achieved while maintaining the SEU protection coverage provided by other classic pipeline protection schemes.

SYSTEM LEVEL SINGLE EVENT UPSET MITIGATION STRATEGIES

2004 ◽  
Vol 14 (02) ◽  
pp. 341-352 ◽  
Author(s):  
W. F. HEIDERGOTT
Keyword(s):  
Systems Engineering ◽  
Fault Tolerant ◽  
Systems Design ◽  
Essential Elements ◽  
Mitigation Strategies ◽  
System Level ◽  
Single Event ◽  
Single Event Upsets ◽  
Fault Masking ◽  
And Performance

Use of a systems engineering process and the application of techniques and methods of fault tolerant systems are applicable to the development of a mitigation strategy for Single Event Upsets (SEU). Specific methods of fault avoidance, fault masking, detection, containment, and recovery techniques are important elements in the mitigation of single event upsets. Fault avoidance through the use of SEU hardened technology, fault masking using coding and redundancy provisions, and solutions applied at the subsystem and system level are available to the system developer. Validation and verification of SEU mitigation and performance of fault tolerance provisions are essential elements of systems design for operation in energetic particle environments.

scholarly journals Study of single event upsets (SEUS) a survey and analysis

2021 ◽  
Author(s):  
Sheldon Mark Foulds
Keyword(s):  
Error Control ◽  
Hamming Code ◽  
Single Event ◽  
Electronic Circuits ◽  
Error Control Coding ◽  
Computing Systems ◽  
Single Event Upsets ◽  
Triple Modular Redundancy ◽  
Radiation Induced ◽  
Modular Redundancy

Over the last few years evolution in electronics technology has led to the shrinkage of electronic circuits. While this has led to the emergence of more powerful computing systems it has also caused a dramatic increase in the occurrence of soft errors and a steady climb in failure in time (FIT) rates. This problem is most prevalent in FPGA based systems which are highly susceptible to radiation induced errors. Depending upon the severity of the problem a number of methods exist to counter these effects including Triple Modular Redundancy (TMR), Error Control Coding (ECC), scrubbing systems etc. The following project presents a simulation of an FPGA based system that employs one of the popular error control code techniques called the Hamming Code. A resulting analysis shows that Hamming Code is able to mitigate the effects of single event upsets (SEUs) but suffers due to a number of limitations.

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