Integration of Al-Fill Processes for Contacts and VIAS

1996 ◽  
Vol 427 ◽  
Author(s):  
H. J. Barth

AbstractToday different Al-fill techniques are used for the fill of submicron contacts and vias. The integration aspects of the most promising approaches, Al-reflow, cold/hot Al-planarization and high pressure Al-fill (Forcefill) are compared to the widely used W-plug technique. The filling properties are discussed with respect to future applications in ULSI devices. Special attention is given to the barrier stability in contacts and the influence on patterning. Various electrical data and reliability results are compared to metallizations with W-plugs. The implications of the Al-fill processes on chip design, especially on the size and shape of holes, the pattern density, the possibility of producing stacked contacts/vias and the metal to contact/via overlap are considered also. In an outlook for future developments, e.g. the introduction of low k dielectrics, the inverse metallization architecture with (dual) damascene interconnects and the emerging Cu metallizations, Alfill processes are facing new challenges which will be discussed.

2013 ◽  
Vol 592-593 ◽  
pp. 563-568
Author(s):  
Christoph Sander ◽  
Martin Gall ◽  
Kong Boon Yeap ◽  
Ehrenfried Zschech

Managing the emerging internal mechanical stress in chips particularly if they are 3D-tscked is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology/flow emerges. This physics-based simulation, however, requires materials parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. Therefore, effective composite-type materials data for several regions of interest are needed. Advanced techniques to measure FEA-and design-relevant properties such as local and effective Youngs modulus and effective CTE values were developed and described in this paper. These data show a clear orientation dependence, caused by the chip design.


2007 ◽  
Vol 134 ◽  
pp. 359-362 ◽  
Author(s):  
Miao Chun Lin ◽  
Mei Qi Wang ◽  
Joe Lai ◽  
Ren Huang ◽  
Cheng Ming Weng ◽  
...  

As 65nm technology in mass production and 45nm technology under development, post etch ash and cleaning faces new challenges with far more stringent requirements on surface cleanliness and materials loss. The introduction and integration of new materials, such as metal hard mask, creates additional requirements for wafer cleaning due to the occurrence of new defect modes related to metal hard mask. We have optimized a post etch ash process and developed a novel aqueous solution (AQ) based single wafer cleaning process to address these new defect modes. Physical characterization results and process integration electrical data are presented in this paper.


2010 ◽  
Vol 97 (10) ◽  
pp. 1241-1262 ◽  
Author(s):  
Yangfan Liu ◽  
Peng Liu ◽  
Yingtao Jiang ◽  
Mei Yang ◽  
Kejun Wu ◽  
...  

Author(s):  
K. Motoyama ◽  
O. van der Straten ◽  
H. Tomizawa ◽  
J. Maniscalco ◽  
S.T. Chen

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