Frequency calibration of the system clock of passive wireless microsystems

This thesis presents a theoretical and simulated study of frequency calibration of the system clock of passive wireless microsystems. The proposed frequency calibration technique achieves ultra-low power, high fre- quency accuracy, and fast calibration of the frequency of a local oscillator in a passive wireless microsystem using a frequency-locked loop (FLL). A new integrating frequency dif- ference detector (iFDD) that senses the frequency difference between the local oscillator and a reference clock is also proposed. The iFDD is implemented using a switched-capacitor network with two integrating paths. The FLL is composed of a logic-control block for gen- eration of clock signals, the iFDD, and a relaxation voltage-controlled oscillator. A detailed analysis of the characteristics of the iFDD in the time and frequency domains is presented. The loop dynamics of the FLL is also investigated. The proposed FLL is implemented in IBM 0.13-µm, 1.2 V CMOS technology and is validated through simulations using Spectre APS.

Frequency calibration of the system clock of passive wireless microsystems

This thesis presents a theoretical and simulated study of frequency calibration of the system clock of passive wireless microsystems. The proposed frequency calibration technique achieves ultra-low power, high fre- quency accuracy, and fast calibration of the frequency of a local oscillator in a passive wireless microsystem using a frequency-locked loop (FLL). A new integrating frequency dif- ference detector (iFDD) that senses the frequency difference between the local oscillator and a reference clock is also proposed. The iFDD is implemented using a switched-capacitor network with two integrating paths. The FLL is composed of a logic-control block for gen- eration of clock signals, the iFDD, and a relaxation voltage-controlled oscillator. A detailed analysis of the characteristics of the iFDD in the time and frequency domains is presented. The loop dynamics of the FLL is also investigated. The proposed FLL is implemented in IBM 0.13-µm, 1.2 V CMOS technology and is validated through simulations using Spectre APS.

A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.