Quantized Decoder Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for a Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor

2018 ◽  
Vol E101.C (8) ◽  
pp. 671-679
Author(s):  
Nobuaki KOBAYASHI ◽  
Tadayoshi ENOMOTO
Keyword(s):  
Supply Voltage ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Dynamic Voltage

scholarly journals Energy Conservation Using Dynamic Voltage Frequency Scaling for Computational Cloud

2016 ◽  
Vol 2016 ◽  
pp. 1-13 ◽  
Author(s):  
A. Paulin Florence ◽  
V. Shanthi ◽  
C. B. Sunil Simon
Keyword(s):  
Resource Sharing ◽  
Time Complexity ◽  
New Technology ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Measured Time ◽  
Dynamic Voltage ◽  
Voltage Frequency ◽  
The Given ◽  
Best Fit

Cloud computing is a new technology which supports resource sharing on a “Pay as you go” basis around the world. It provides various services such as SaaS, IaaS, and PaaS. Computation is a part of IaaS and the entire computational requests are to be served efficiently with optimal power utilization in the cloud. Recently, various algorithms are developed to reduce power consumption and even Dynamic Voltage and Frequency Scaling (DVFS) scheme is also used in this perspective. In this paper we have devised methodology which analyzes the behavior of the given cloud request and identifies the associated type of algorithm. Once the type of algorithm is identified, using their asymptotic notations, its time complexity is calculated. Using best fit strategy the appropriate host is identified and the incoming job is allocated to the victimized host. Using the measured time complexity the required clock frequency of the host is measured. According to that CPU frequency is scaled up or down using DVFS scheme, enabling energy to be saved up to 55% of total Watts consumption.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

Effectiveness of DFS Tuning on Java Server Workload

2015 ◽  
Vol 25 (01) ◽  
pp. 1640005 ◽  
Author(s):  
Hitoshi Oi
Keyword(s):  
Power Consumption ◽  
Sampling Period ◽  
Threshold Level ◽  
Load Level ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Dynamic Frequency Scaling ◽  
Maximum Reduction ◽  
Dynamic Frequency

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5[Formula: see text]s) reduced the power by 6[Formula: see text]Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10[Formula: see text]Watt. In jbb05, stretching the sampling period was only effective up to 0.5[Formula: see text]s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05.

Sign in / Sign up

Export Citation Format

Share Document