A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

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Effectiveness of DFS Tuning on Java Server Workload

Journal of Circuits System and Computers ◽

10.1142/s0218126616400053 ◽

2015 ◽

Vol 25 (01) ◽

pp. 1640005 ◽

Cited By ~ 1

Author(s):

Hitoshi Oi

Keyword(s):

Power Consumption ◽

Sampling Period ◽

Threshold Level ◽

Load Level ◽

Clock Frequency ◽

Frequency Scaling ◽

Dynamic Frequency Scaling ◽

Maximum Reduction ◽

Dynamic Frequency

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5[Formula: see text]s) reduced the power by 6[Formula: see text]Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10[Formula: see text]Watt. In jbb05, stretching the sampling period was only effective up to 0.5[Formula: see text]s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05.

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A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing

Electronics ◽

10.3390/electronics9122033 ◽

2020 ◽

Vol 9 (12) ◽

pp. 2033

Author(s):

Ahmed Elgreatly ◽

Ahmed Dessouki ◽

Hassan Mostafa ◽

Rania Abdalla ◽

El-sayed El-Rabaie

Keyword(s):

Power Consumption ◽

Software Defined Radio ◽

Dynamic Range ◽

Supply Voltage ◽

Cmos Technology ◽

The Body ◽

Analog To Digital Converters ◽

Clock Frequency ◽

Analog To Digital ◽

Operation Speed

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

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Design and Implementation of a High Accuracy Interpolation Encoder IC for Magnetic Sensor

ASME 2019 28th Conference on Information Storage and Processing Systems ◽

10.1115/isps2019-7476 ◽

2019 ◽

Author(s):

Wen-Yu Chen ◽

Yi-Feng Zhang ◽

Paul C.-P. Chao ◽

Eka Fitrah Pribadi

Keyword(s):

Measurement System ◽

Noise Immunity ◽

Supply Voltage ◽

High Accuracy ◽

Cmos Process ◽

Specific Method ◽

Clock Frequency ◽

Design And Implementation ◽

Equal Distance ◽

Interpolation Technique

Abstract The magnetic encoder (ME) always employs sensor passing through periodic and equal distance grating and then generates periodic quadrature scaling signals for displacement measurement. The phase is relative to the movement. To improve encoder accuracy or resolution, electronic interpolation technique had been developed to subdivide the phase of quadrature scaling signals. According to the trends, this paper proposed a specific method with excellent noise immunity characteristic and a complete calibration process to improve the accuracy of the system. The designed circuit is taped-out using TSMC 0.18-μm CMOS process, where the active area is 1643 μm × 1676 μm. The chip has the specification of 3.3 V supply voltage, 20 MHz clock frequency, and 0.0859 mW power consumption. The accuracy of the measurement system is 1.065um.

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A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Electronics ◽

10.3390/electronics10070860 ◽

2021 ◽

Vol 10 (7) ◽

pp. 860

Author(s):

Shao-Ku Kao

Keyword(s):

Duty Cycle ◽

Delay Line ◽

Supply Voltage ◽

Cmos Process ◽

Delay Lines ◽

Clock Frequency ◽

Quantization Method ◽

Total Delay ◽

Chip Area ◽

Measurement Results

This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm2, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.

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TEMPERATURE-ADAPTIVE ENERGY REDUCTION TECHNIQUES FOR NANO-CMOS CIRCUITS DISPLAYING REVERSED TEMPERATURE DEPENDENCE

Journal of Circuits System and Computers ◽

10.1142/s0218126608004393 ◽

2008 ◽

Vol 17 (03) ◽

pp. 423-438 ◽

Cited By ~ 1

Author(s):

RANJITH KUMAR ◽

VOLKAN KURSUN

Keyword(s):

Energy Consumption ◽

Threshold Voltage ◽

Elevated Temperatures ◽

Supply Voltage ◽

Energy Reduction ◽

Cmos Circuits ◽

Clock Frequency ◽

Active Mode ◽

Voltage Tuning ◽

Body Bias

Temperature dependent propagation delay characteristics of CMOS circuits will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 32nm CMOS technology is enhanced when the temperature is increased at the nominal supply and threshold voltages. The enhancement of circuit speed provides new opportunities to lower the energy consumed by active circuits at elevated temperatures. Temperature-adaptive supply and threshold voltage tuning techniques are proposed in this paper to reduce the high temperature energy consumption without degrading the clock frequency in the active mode. Results indicate that the energy consumption can be lowered by up to 21% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body-bias exponentially reduces the leakage currents as well as the parasitic junction capacitances of the MOSFETs. The temperature-adaptive threshold voltage tuning through reverse body-bias yields an active mode energy reduction by up to 29.8% as compared to the standard zero-body-biased circuits at high temperatures.

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Green Queue: Customized Large-Scale Clock Frequency Scaling

2012 Second International Conference on Cloud and Green Computing ◽

10.1109/cgc.2012.62 ◽

2012 ◽

Cited By ~ 23

Author(s):

Ananta Tiwari ◽

Michael Laurenzano ◽

Joshua Peraza ◽

Laura Carrington ◽

Allan Snavely

Keyword(s):

Large Scale ◽

Clock Frequency ◽

Frequency Scaling

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MODEL-DRIVEN CLOCK FREQUENCY SCALING FOR CONTROL-DOMINATED EMBEDDED SYSTEMS

International Journal of Computing ◽

10.47839/ijc.7.2.516 ◽

2014 ◽

pp. 100-107

Author(s):

Zdravko Karakehayov

Keyword(s):

Power Management ◽

Rate Control ◽

Power Saving ◽

Clock Frequency ◽

Frequency Scaling ◽

Clock Rate ◽

Battery Lifetime ◽

Model Driven ◽

Optimal Value

This paper introduces a combination of models and proofs for optimal power management via clock frequency scaling. The approach is suitable for systems on a chip or microcontrollers where a processor runs in parallel with embedded peripherals. Since the methodology is based on clock rate control, it is very easy to implement. A hardware model, a computational model and an energy model underlie the procedure. We proved that the combination of models is sufficient to determine an optimal clock rate for the CPU. Furthermore, we expand the application space taking into account preemption of tasks. Also, we discuss the role of embedded peripherals when select the clock frequency in both active and power-saving modes. Simulation results manifest the benefits of clock rate control under the proposed methodology. An example shows a 56% increase of the battery lifetime when the clock rate is changed from the lowest possible level to the optimal value.

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