ADVANCED HIGH-PERFORMANCE RECONFIGURABLE COMPUTERS WITH IMMERSION COOLING

Author(s):  
I.I. Levin ◽  
A. M. Fedorov ◽  
Y. I. Doronchenko ◽  
M.K. Raskladkin
Author(s):  
Jimmy Chuang ◽  
Jin Yang ◽  
David Shia ◽  
Y L Li

Abstract In order to meet increasing performance demand from high-performance computing (HPC) and edge computing, thermal design power (TDP) of CPU and GPU needs to increase. This creates thermal challenge to corresponding electronic packages with respect to heat dissipation. In order to address this challenge, two-phase immersion cooling is gaining attention as its primary mode of heat of removal is via liquid-to-vapor phase change, which can occur at relatively low and constant temperatures. In this paper, integrated heat spreader (IHS) with boiling enhancement features is proposed. 3D metal printing and metal injection molding (MIM) are the two approaches used to manufacture the new IHS. The resultant IHS with enhancement features are used to build test vehicles (TV) by following standard electronic package assembly process. Experimental results demonstrated that boiling enhanced TVs improved two-phase immersion cooling capability by over 50% as compared to baseline TV without boiling enhanced features.


Author(s):  
Shuai Shao ◽  
Tianyi Gao ◽  
Huawei Yang ◽  
Jie Zhao ◽  
Jiajun Zhang

Abstract Along with advancements in microelectronics packaging, the power density of processor units has steadily increased over time. Data center servers equipped for high performance computing (HPC) often use multiple central processing units (CPUs) and graphical processing units (GPUs), thereby resulting in an increased power density, exceeding 1 kW per U. Many data center organizations are evaluating single phase immersion technology as a potential energy and resource saving cooling option. In this work immersion cooling was studied at a power level of 2.7kW/U with a 5U-height immersion cooling tank. Heat generated by a simulated GPU server was transferred to the secondary loop coolant, and then exchanged with the primary loop facility coolant through the heat exchanger. The chiller supply and return temperature and flow rate was controlled for the primary loop. The simulated GPU server chassis was designed to provide thermal power equivalent to a high power density server. Eight simulated power heaters, of which each unit was the size of a GPU chipset, was assembled in the comparable location to a real IT equipment on a 4U server chassis. Power for the GPU simulated chassis was able to support up to 2700 W maximum. Three investigations for this immersion cooling system evaluation were performed through comprehensive testing. The first is to identify the key decision making factor(s) for evaluating the thermal performance of 4 hydrocarbon-based dielectric coolants, including power parametric analysis, transient analysis, power cycling test, and fluid temperature profiling. The second is to develop an optimization strategy for the immersion system thermal performance. The third is to verify the capability of an 1U heat sink to support high density processor units over 300 W per GPU in an immersion cooling solution.


2009 ◽  
Vol 2009 ◽  
pp. 1-9
Author(s):  
Manuel Saldaña ◽  
Emanuel Ramalho ◽  
Paul Chow

High-performance reconfigurable computers (HPRCs) provide a mix of standard processors and FPGAs to collectively accelerate applications. This introduces new design challenges, such as the need for portable programming models across HPRCs and system-level verification tools. To address the need for cosimulating a complete heterogeneous application using both software and hardware in an HPRC, we have created a tool called the Message-passing Simulation Framework (MSF). We have used it to simulate and develop an interface enabling an MPI-based approach to exchange data between X86 processors and hardware engines inside FPGAs. The MSF can also be used as an application development tool that enables multiple FPGAs in simulation to exchange messages amongst themselves and with X86 processors. As an example, we simulate a LINPACK benchmark hardware core using an Intel-FSB-Xilinx-FPGA platform to quickly prototype the hardware, to test the communications. and to verify the benchmark results.


1999 ◽  
Author(s):  
Michael P. Caffrey ◽  
John J. Szymanski ◽  
A. Begtrup ◽  
J. Layne ◽  
T. Nelson ◽  
...  

2022 ◽  
Vol 15 (3) ◽  
pp. 1-20
Author(s):  
Christian Lienen ◽  
Marco Platzner

Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS , a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.


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