Partitioned Heat Sinks for Improved Natural Convection

The main drivers contributing to the continued growth of network traffic include video, mobile broadband and machine-to-machine communication (Internet of Things, cloud computing, etc.). Two primary technologies that next-generation (5G) networks are using to increase capacity to meet these future demands are massive MIMO (Multi-Input Multi-Output) antenna arrays and new frequency spectrum. The massive MIMO antenna arrays have significant thermal challenges due to the presence of large arrays of active antenna elements coupled with a reliance on natural convection cooling using vertical plate-finned heat sinks. The geometry of vertical plate-finned heat sinks can be optimized (for example, by choosing the fin pitch and thickness that minimize the thermal resistance of the heat sink to ambient air) and enhanced (for example, by embedding heat pipes within the base to improve heat spreading) to improve convective heat transfer. However, heat transfer performance often suffers as the sensible heat rise of the air flowing through the heat sink can be significant, particularly near the top of the heat sink; this issue can be especially problematic for the relatively large or high-aspect-ratio heat sinks associated with massive MIMO arrays. In this study a vertical plate-finned natural convection heat sink was modified by partitioning the heat sink along its length into distinct sections, where each partitioned section ejects heated air and entrains cooler air. This approach increases overall heat sink effectiveness as the net sensible heat rise of the air in any partitioned section is less than that observed in the unpartitioned heat sink. Experiments were performed using a standard heat sink and equivalent heat sinks partitioned into two and three sections for the cases of ducted and un-ducted natural convection with a uniform heat load applied to the rear of the heat sink. Numerical models were developed which compare well to the experimental results and observed trends. The numerical models also provide additional insight regarding the airflow and thermal performance of the partitioned heat sinks. The combined experimental and numerical results show that for relatively tall natural convection cooled heat sinks, the partitioning approach significantly improves convective heat transfer and overall heat sink effectiveness.

Ultra-Compact Micro-Scale Heat Exchanger for Advanced Thermal Management in Datacenters

The present study is focused on the experimental characterization of two-phase heat transfer performance and pressure drops within an ultra-compact heat exchanger (UCHE) suitable for electronics cooling applications. In this specific work, the UCHE prototype is anticipated to be a critical component for realizing a new passive two-phase cooling technology for high-power server racks, as it is more compact and lighter weight than conventional heat exchangers. This technology makes use of a novel combination of thermosyphon loops, at the server-level and rack-level, to passively cool an entire rack. In the proposed two-phase cooling technology, a smaller form factor UCHE is used to transfer heat from the server-level thermosyphon cooling loop to the rack-level thermosyphon cooling loop, while a larger form factor UCHE is used to reject the total heat from the server rack into the facility-level cooling loop. The UCHE is composed of a double-side-copper finned plate enclosed in a stainless steel enclosure. The geometry of the fins and channels on both sides are optimized to enhance the heat transfer performance and flow stability, while minimizing the pressure drops. These features make the UCHE the ideal component for thermosyphon cooling systems, where low pressure drops are required to achieve high passive flow circulation rates and thus achieve high critical heat flux values. The UCHE’s thermal-hydraulic performance is first evaluated in a pump-driven system at the Laboratory of Heat and Mass Transfer (LTCM-EPFL), where experiments include many configurations and operating conditions. Then, the UCHE is installed and tested as the condenser of a thermosyphon loop that rejects heat to a pumped refrigerant system at Nokia Bell Labs, in which both sides operate with refrigerants in phase change (condensation-to-boiling). Experimental results demonstrate high thermal performance with a maximum heat dissipation density of 5455 (kW/m3/K), which is significantly larger than conventional air-cooled heat exchangers and liquid-cooled small pressing depth brazed plate heat exchangers. Finally, a thermal performance analysis is presented that provides guidelines in terms of heat density dissipations at the server- and rack-level when using passive two-phase cooling.

Experimental Validation and Design Simulations of a Passive Two-Phase Cooling System for Datacenters

Thermosyphon cooling systems represent the future of datacenter cooling, and electronics cooling in general, as they provide high thermal performance, reliability and energy efficiency, as well as capture the heat at high temperatures suitable for many heat reuse applications. On the other hand, the design of passive two-phase thermosyphons is extremely challenging because of the complex physics involved in the boiling and condensation processes; in particular, the most important challenge is to accurately predict the flow rate in the thermosyphon and thus the thermal performance. This paper presents an experimental validation to assess the predictive capabilities of JJ Cooling Innovation’s thermosyphon simulator against one independent data set that includes a wide range of operating conditions and system sizes, i.e. thermosyphon data for server-level cooling gathered at Nokia Bell Labs. Comparison between test data and simulated results show good agreement, confirming that the simulator accurately predicts heat transfer performance and pressure drops in each individual component of a thermosyphon cooling system (cold plate, riser, evaporator, downcomer (with no fitting parameters), and eventually a liquid accumulator) coupled with operational characteristics and flow regimes. In addition, the simulator is able to design a single loop thermosyphon (e.g. for cooling a single server’s processor), as shown in this study, but also able to model more complex cooling architectures, where many thermosyphons at server-level and rack-level have to operate in parallel (e.g. for cooling an entire server rack). This task will be performed as future work.

Feature Vector Identification and Prognostics of SAC305 PCB’s for Varying Conditions of Temperature and Vibration Loads

This study focuses on the feature vector identification of SAC305 solder alloy PCB’s of two different configurations during varying conditions of temperature and vibration. The feature vectors are identified from the strain signals, that are acquired from four symmetrical locations of the PCB at regular intervals during vibration. The changes in the vibration characteristics of the PCB are characterized by three different types of experiments. First type of analysis emphasizes the vibration characteristic for varying conditions of acceleration levels keeping the temperature constant during vibration. The second analysis studies the characteristics changes for varying temperature levels by keeping the acceleration levels constant. Finally, the third analysis focuses on the combined changes in temperature and acceleration levels for the board during vibration. The above analyses try to imitate the actual working conditions of an electronic board in an automobile which is subjected to varying environments of temperature and vibration. The strain signals acquired during each of these experiments are compared based on both time and frequency domain characteristics. Different statistical and frequency based techniques were used to identify the variations in the strain signal with changes in the environment and loading conditions. The feature vectors of failure at a constant working condition and load were identified and as an extension to the previous work, the effectiveness of the feature vectors during these varying conditions of temperature and acceleration levels are investigated using the above analyses. The feature vector of a PCB under varying conditions of temperature and load are identified and compared with different operating environments.

Reliability Assessment of Cu-Al WB Under High Temperature and High Voltage Bias Application

Electronics in automotive underhood environments may be subjected to high temperature in the range of 125–200°C. Transition to electric vehicles has resulted in need for electronics capable of operation under high voltage bias. Automotive electronics has simultaneously transitioned to copper wire-bond from gold wire-bond for first-level interconnections. Copper has a smaller process window and a higher propensity for corrosion in comparison with gold wire bonds. There is scarce information on the reliability of copper wire bonds in presence of high voltage bias under operation at high temperature. In this paper, a multiphysics model for micro galvanic corrosion in the presence of chlorine is introduced. The diffusion cell is used to measure the diffusivity of chlorine in different pH values and different temperatures. Diffusivity measurements are incorporated into the 3D ionic transport model to study the effect of different environmental factors on the transport rate of chlorine. The tafel parameters for copper, aluminum and intermetallics have been extracted through measurements of the polarization curves. The multiple physics of ionic transport in presence of concentration gradient, potential gradient is coupled with the galvanic corrosion.

Experimental Study of Crack Propagation at the PCB/Underfill Interface due to Thermal Aging

Flip-Chip Ball Grid Arrays (FCBGAs) are finding applications in automotive underhood electronics for enablement of safety-critical functions. Underfills needed to reinforce flip-chip interconnects in FCBGAs need to operate reliably under sustained high temperature operation. Underfill-to-substrate interface is one of the primary failure locations under wide thermal excursions and usually a precursor to flip-chip joint failure. In order to assess the reliability in the end application, there is need for understanding the damage progression of the underfill-to-substrate interface as a function of operating time and operating temperature. In this study, the Substrate-UF interface was exposed to high temperature and the interfacial fracture toughness quantified. A three-point composite beam specimen of PCB/Underfill was fabricated to study the interface and thermally aged for periods of 10 days, 30 days, 60 days at temperatures ranging from 100°C to 150°C. Quasi-static bending was used to observe and determine interfacial delamination of the sample specimen. A 2D-Digital Image Correlation (DIC) method was also employed to understand the Crack tip opening displacement (CTOD), crack initiation and the fracture toughness, CTOD were compared with the aging schedule and temperature.

Evaluation of Single Phase Immersion Cooling System for High Performance Server Chassis Using Dielectric Coolants

Along with advancements in microelectronics packaging, the power density of processor units has steadily increased over time. Data center servers equipped for high performance computing (HPC) often use multiple central processing units (CPUs) and graphical processing units (GPUs), thereby resulting in an increased power density, exceeding 1 kW per U. Many data center organizations are evaluating single phase immersion technology as a potential energy and resource saving cooling option. In this work immersion cooling was studied at a power level of 2.7kW/U with a 5U-height immersion cooling tank. Heat generated by a simulated GPU server was transferred to the secondary loop coolant, and then exchanged with the primary loop facility coolant through the heat exchanger. The chiller supply and return temperature and flow rate was controlled for the primary loop. The simulated GPU server chassis was designed to provide thermal power equivalent to a high power density server. Eight simulated power heaters, of which each unit was the size of a GPU chipset, was assembled in the comparable location to a real IT equipment on a 4U server chassis. Power for the GPU simulated chassis was able to support up to 2700 W maximum. Three investigations for this immersion cooling system evaluation were performed through comprehensive testing. The first is to identify the key decision making factor(s) for evaluating the thermal performance of 4 hydrocarbon-based dielectric coolants, including power parametric analysis, transient analysis, power cycling test, and fluid temperature profiling. The second is to develop an optimization strategy for the immersion system thermal performance. The third is to verify the capability of an 1U heat sink to support high density processor units over 300 W per GPU in an immersion cooling solution.

Development of Process-Recipes for Multi-Layer Circuitry Printing With Z-Axis Interconnects Using Aerosol-Jet Nanoparticle Ink

Flexible electronics is a rapid emerging trend in consumer-electronics with ever-increasing applications showing feasibility of functionality with flexibility. Aerosol Jet printing technology has gained rapid acceptance for additive printing owing to non-contact deposition and ability to print on non-planar surfaces. Prior work on aerosol-jet print processes primarily focuses on single-layer printing, taking into account different parameters such as mass flow, line width, sintering conditions, and overspray. Flexible PCBs in complex applications are envisioned to be multi-layered, involving stacking of interconnections and connection between successive layers through use of z-axis connections. Aerosol-jet printing method allows the printing of interconnections with a number of inks including silver, copper, and carbon with fine lines and spaces in neighborhood of 10μm. Process recipes for manufacturing multilayer circuits and system scale-up methods are required. The objective of the paper is to establish process-recipes for z-axis interconnects and quantify process variability with Aerosol-jet print process needed for high volume scale-up. Conductive interconnects have been printed using the ultrasonic atomizer and the interlayer dielectrics have been printed using the pneumatic atomizer. The effect of thermal sintering on the performance of the printed circuits has been quantified through measurements of interconnect resistance and shear load to failure. This paper explores the printing of multi-layer upto 8 conductive layers. Sintering profile for lower resistance per unit length and higher shear load to failure was tested.

Comparative Study of Effective Cooling in Microchannel Heat Sinks (MCHS) With Nanofluid and Hydrophobic Nanostructures Using Computational Fluid Dynamics

The goal of this research is to present an analytical model of nanostructures and study the effects of their geometry on the performance of micro channels. The pressure drop experienced by micro channels is of interest as it presents a limit on forced convection heat transfer. This work will demonstrate how the presence of nanostructures primarily affects pressure drop as well as other cooling flow characteristics. Additional work in the impact of microchannel cross-sectional geometry and friction factor formulation is provided as well. Multiple transient analyses were performed in ANSYS FLUENT to ascertain performance characteristics of microchannels without the presence of hydrophobic nanostructures. The results were compared to the analytical model developed in this study.

Deformation Behavior of SAC305 Solder Joints With Multiple Grains

Lead-free solder joints are the most widely used interconnects in electronic packaging industries. Usually solder joints in most of the electronic devices are exposed to an environment where variation of temperature exists, which indicates cyclic thermal loading to be a very common type of external loading. Moreover, due to difference in the coefficient of thermal expansion (CTE) among dissimilar contact materials, shear stress develops in junctions under thermal loading, which significantly deteriorates the overall reliability. Hence, characterization of lead-free solder materials under thermal loading is essential to predict the performance and deformation behavior of joints in practical applications. A significant portion of the studies in this field are concerned with thermal loading of lead-free solder interconnects, each of which has a very small diameter, in sub-millimeter range. Although the solder balls have very small dimensions, most of the analyses considered them as a bulk material with homogeneous and isotropic properties. However, with the decrease of specimen dimensions, size effects and material directionality play a significant role in deformation mechanisms. Since a very few grains exist in a small specimen, individual grain properties play a vital role on overall material response. Therefore, modeling from the grain structure and orientation point of view could be an effective and more accurate way to predict solder joint deformation behavior under thermal loading. In this study, the effect of grain size and orientation of SAC305 is investigated for predicting anisotropic behavior of solder joints under thermal load. A simplified three-dimensional model of beach-ball configuration solder joint was generated and simulated using ABAQUS finite element (FE) software. Experimentally obtained directional properties such as elastic modulus and CTE were assigned to the computational geometry to create material anisotropy. The effects of material anisotropy were studied for varying grain size specimens, as well as for specimens with varying grain orientation.