The Power Analysis of 1T-DRAM Cell with Different FET technologies

Mapping Intimacies ◽

10.21203/rs.3.rs-477489/v1 ◽

2021 ◽

Author(s):

Durgesh Addala ◽

Sanjeet Kumar Sinha ◽

Gadiparthi Mohan Chandu

Keyword(s):

Low Power ◽

Power Dissipation ◽

Power Analysis ◽

Portable Power ◽

Low Power Circuits ◽

Power Circuits ◽

Model Structures ◽

Day By Day

Abstract DRAM’s are essential for memory-based electronics devices and the usage of RAM is increasing day by day to reach the user's expectation the products are get designed based on low power and portable. Power dissipation is a major issue to solve this issue researchers are focusing on low power circuits and trying to design the circuits with less number of the transistor so that it will consume less amount of power. In this paper, three structures are presently based on MOSFET technology and CNTFET technology. MOSFET model structures are divided into two they are 1.DRAM circuit with Tri-state buffers and 2. DRAM circuit without Tri-state buffers. CNTFET based structure is built with the help of ‘CarbonNanoTube-FET’s and the structure is the same as DRAM without Tri-state buffers. Power analysis, voltage, delay are evaluated with the help of cadence virtuoso and LTspice Tools.

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Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.203.469 ◽

2012 ◽

Vol 203 ◽

pp. 469-473

Author(s):

Ruei Chang Chen ◽

Shih Fong Lee

Keyword(s):

Low Power ◽

High Performance ◽

Low Voltage ◽

Design Flow ◽

Total Power ◽

Cmos Process ◽

Low Power Circuits ◽

Class D ◽

Total Power Consumption ◽

Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

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W2B: High Performance Low Power Circuits

2018 31st IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2018.8618573 ◽

2018 ◽

Keyword(s):

Low Power ◽

High Performance ◽

Low Power Circuits ◽

Power Circuits

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Design of high performance, low power sub thresholds ram using source coupled logic for implantable applications.

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.12.11280 ◽

2018 ◽

Vol 7 (2.12) ◽

pp. 205

Author(s):

T Vasudeva Reddy ◽

Dr B.K. Madhavi

Keyword(s):

Low Power ◽

High Performance ◽

Supply Voltage ◽

Process Variations ◽

Primary Objective ◽

Total Power ◽

Threshold Region ◽

Major Power ◽

Low Power Circuits ◽

Power Circuits

Low power circuits functioning in sub threshold were proposed in earlier seventies. Recently, growing with the need of low power consumption, the low power circuits have became more attractive. However, the act of sub threshold design logics has become sensitive to the supply voltage & process variations like temperature and so on. In sub threshold region of operations the supply voltage (Vgs) is less than the threshold (Vth).This leads to less power dissipation in over all circuit, but drastically increment in propagation delay. The major intention of the paper is to offer new low power & less delay digital circuits. SRAM is the major power drawing element and dissipation is about 40% in total power. The primary objective is to design of sub threshold SRAM design, Functionality and performance is estimated from the power and delay.The second objective is to offer novel Source coupled logic based SRAM (ST-SC SRA) M & Operating these design under sub threshold operating region. Performance is analyzed through power and delay. Finally comparing the traditional sub threshold SRAM with source coupled based SRAM in power and delay on par with the performance. Discussing some of the applications, where there is a requirement of less power and delay.

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