Verification of connectivity of electrical connections in topology of radio electronic equipment products
The solution of the problem of verifying the connectivity of electrical connections in the VLSI topology is considered. Effective use of computing resources is based on the use of quasi‑linear computational (temporal and capacitive) complexity of algorithms: sweeping the plane of a straight line for constructing a graph of electrical connections; allocation of subsets of connected vertices in the components of the connection of an undirected graph of large dimension for the determination of electrically connected contacts; establish isomorphism of component‑full colored graphs for comparing the restored list with the original list of electrical connections The proposed solution has a time complexity O(N + N log2 N ) and the capacitive complexity O(s + N ), where N is the number of elements in the topology and s is the number of contacts in the source circuit.