scholarly journals Secured Application Environment using Enhanced Graphical Passwords

2021 ◽  
Vol 9 (VI) ◽  
pp. 1462-1469
Author(s):  
Ms. Prajakta Vikhe
Keyword(s):  
Advanced Encryption Standard ◽  
Public Cloud ◽  
Main Application ◽  
Graphical Passwords ◽  
Aes Algorithm ◽  
Hash Code ◽  
Ascii Code ◽  
The One ◽  
Hashing Algorithm ◽  
Authentication Technique

Today computer and mobile based applications has become an integral part of our life. Thus, there arises a need of a reliable security while using these applications using authentication techniques that are most secured and hard to crack. Today many authentication techniques are introduced for better security and replace textual authentication technique. But these techniques are proving insufficient, so new ways should be studied and introduced for better security. So, we are concentrating on two such techniques, first we studied graphical authentication systems using images. The one such technique called gRat which uses set of images for authentication was found to be useful. The second for searching a different authentication technique we came across ENP which explains how to provide security using to an application by using hashing, ascii, negation and cryptography together for a secured application. So, we find out that one technique is insufficient and more than two techniques should be combined together. So, in this paper we are recommending a dual authentication technique. First technique will be used for login id and other will be used for login password. The first technique uses a set of images with specific border colors for authentication and is called Graphical random authentication technique (gRat). In this technique a set of images with different boundary colors are displayed for the user which are shown randomly each time a user attempts a login ID. The user has to select the same set of images with same boundary color in same format for login ID verification than only second technique for login password will be shown. The second technique uses encryption and negative password together called as Encrypted negative password (ENP). In this technique while deciding a password a plain textual password is accepted from the user and then it is converted to hash code using hashing algorithm. Then the hash code is converted to an ascii code od 0’s and 1’s. Then negation is applied to the ascii where we get a negative text. The negative text is then encrypted. This process is followed in reverse while authentication. After second correct verification main application will be started. Both authentication data will be secured by Advanced encryption standard (AES) algorithm and saved on cloud. We are using public cloud Google drive as our cloud as it is free and more secured. Thus, while testing the application for authentication using both techniques together our system becomes very secured and almost unbreakable.

scholarly journals Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

10.29007/x3tx ◽  
2019 ◽  
Author(s):  
Luka Daoud ◽  
Fady Hussein ◽  
Nader Rafla
Keyword(s):  
High Level Synthesis ◽  
Advanced Encryption Standard ◽  
Data Confidentiality ◽  
Maximum Throughput ◽  
Loop Unrolling ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
High Level ◽  
Dedicated Hardware ◽  
Vivado Hls

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

AES Enhanced by Output Feedback Block Mode Operation

2020 ◽  
Vol 1 (1) ◽  
pp. 11-22
Author(s):  
Asaad A. Hani
Keyword(s):  
Output Feedback ◽  
Data Security ◽  
New Technology ◽  
Advanced Encryption Standard ◽  
The Internet ◽  
Secret Key ◽  
Aes Algorithm ◽  
Mode Operation ◽  
Federal Information Processing Standard ◽  
Exclusive Or

There is a great research in the field of data security these days. Storing information digitally in the cloud and transferring it over the internet proposes risks of disclosure and unauthorized access; thus, users, organizations, and businesses are adapting new technology and methods to protect their data from breaches. In this paper, we introduce a method to provide higher security for data transferred over the internet, or information based in the cloud. The introduced method for the most part depends on the Advanced Encryption Standard (AES) algorithm, which is currently the standard for secret key encryption. A standardized version of the algorithm was used by The Federal Information Processing Standard 197 called Rijndael for the AES. The AES algorithm processes data through a combination of exclusive-OR operations (XOR), octet substitution with an S-box, row and column rotations, and MixColumn operations. The fact that the algorithm could be easily implemented and run on a regular computer in a reasonable amount of time made it highly favorable and successful. In this paper, the proposed method provides a new dimension of security to the AES algorithm by securing the key itself such that even when the key is disclosed; the text cannot be deciphered. This is done by enciphering the key using Output Feedback Block Mode Operation. This introduces a new level of security to the key in a way, in which deciphering the data requires prior knowledge of the key and the algorithm used to encipher the key for the purpose of deciphering the transferred text.

CompactRIO Based Real Time Implementation of AES Algorithm for Embedded Applications

2019 ◽  
Vol 10 (2) ◽  
pp. 19-36
Author(s):  
El Adib Samir ◽  
Raissouni Naoufal
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Software Design ◽  
System Architecture ◽  
Advanced Encryption Standard ◽  
Time Cost ◽  
Security Applications ◽  
Aes Algorithm ◽  
Embedded Applications ◽  
Different Levels

For real-time embedded applications, several factors (time, cost, power) that are moving security considerations from a function-centric perspective into a system architecture (hardware/software) design issue. The National Institute of Standards and Technology (NIST) adopts Advanced Encryption Standard (AES) as the most widely used encryption algorithm in many security applications. The AES algorithm specifies 10, 12 and 14 rounds offering different levels of security. Although the number of rounds determines the strength of security, the power consumption issue has risen recently, especially in real-time embedded systems. In this article, the authors present real time implementation of the AES encryption on the compactRIO platform for a different number of AES rounds. The target hardware is NI cRIO-9022 embedded real-time controller from National Instruments (NI). The real time encryption processing has been verified successfully. The power consumption and encryption time experimental results are presented graphically for 10, 12 and 14 rounds of processing.

scholarly journals Modified Advanced Encryption Standard Algorithm for Information Security

Symmetry ◽  
2019 ◽  
Vol 11 (12) ◽  
pp. 1484 ◽  
Author(s):  
Oluwakemi Christiana Abikoye ◽  
Ahmad Dokoro Haruna ◽  
Abdullahi Abubakar ◽  
Noah Oluwatobi Akande ◽  
Emmanuel Oluwatobi Asani
Keyword(s):  
Execution Time ◽  
Advanced Encryption Standard ◽  
Avalanche Effect ◽  
Plain Text ◽  
Aes Algorithm ◽  
Cipher Text ◽  
Encryption And Decryption ◽  
To Come ◽  
Cryptographic Techniques ◽  
Modified Aes

The wide acceptability of Advanced Encryption Standard (AES) as the most efficient of all of the symmetric cryptographic techniques has further opened it up to more attacks. Efforts that were aimed at securing information while using AES is still being undermined by the activities of attackers This has further necessitated the need for researchers to come up with ways of enhancing the strength of AES. This article presents an enhanced AES algorithm that was achieved by modifying its SubBytes and ShiftRows transformations. The SubBytes transformation is modified to be round key dependent, while the ShiftRows transformation is randomized. The rationale behind the modification is to make the two transformations round key dependent, so that a single bit change in the key will produce a significant change in the cipher text. The conventional and modified AES algorithms are both implemented and evaluated in terms avalanche effect and execution time. The modified AES algorithm achieved an avalanche effect of 57.81% as compared to 50.78 recorded with the conventional AES. However, with 16, 32, 64, and 128 plain text bytes, the modified AES recorded an execution time of 0.18, 0.31, 0.46, and 0.59 ms, respectively. This is slightly higher than the results obtained with the conventional AES. Though a slightly higher execution time in milliseconds was recorded with the modified AES, the improved encryption and decryption strength via the avalanche effects measured is a desirable feat.

Regulations and Standards in Public Cloud

2020 ◽  
Vol 13 (3) ◽  
pp. 21-36
Author(s):  
Jitendra Singh ◽  
Kamlesh Kumar Raghuvanshi
Keyword(s):  
Data Center ◽  
Critical Issue ◽  
Regulatory Compliance ◽  
Cloud Provider ◽  
Security Threats ◽  
Public Cloud ◽  
The Public ◽  
Regulatory Standards ◽  
The One ◽  
Security Standards

Security is a critical issue particularly in public cloud as it rests with the cloud providers. During security implementation, prevailing security threats and regulatory standards are borne in mind. Regulatory compliance varies from one cloud provider to another according to their maturity and location of the data center. Thus, subscribers need to verify the security requirement meeting their objective and the one implemented by the public cloud provider. To this end, subscribers need to visit each cloud provider's site to view the compliance. This is a time-consuming activity at the same time difficult to locate on a website. This work presents the prominent security standards suggested by the leading security institutions including NIST, CSA, ENISA, ISO, etc., that are applicable to the public cloud. A centrally-driven scheme is proposed in order to empower the subscriber to know the regulation and standards applicable according to their services need. The availability of an exhaustive list at one place will lower the users hassle at subscription time.

Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications

2016 ◽  
Vol 25 (07) ◽  
pp. 1650080 ◽  
Author(s):  
Raed Bani-Hani ◽  
Khaldoon Mhaidat ◽  
Salah Harb
Keyword(s):  
Low Power ◽  
Area Ratio ◽  
Advanced Encryption Standard ◽  
Fpga Design ◽  
Power Efficient ◽  
Aes Algorithm ◽  
Lookup Tables ◽  
Small Footprint ◽  
Embedded Applications

In this paper, a very compact and efficient 32-bit FPGA design for the Advanced Encryption Standard (AES) algorithm is presented. The design is very well suited for small foot-print low-power embedded applications. The design is validated and synthesized using the Xilinx ISE Design Suite. To the best of our knowledge, our design is the most efficient in terms of throughput to area ratio and requires the smallest number of lookup tables (LUTs), logic slices, and registers. It also achieves the highest throughput among designs that do not use DSPs. It is also very power-efficient; it can process more than 10 Gbps/W on Kintex-7 FPGA.

Sign in / Sign up

Export Citation Format

Share Document