scholarly journals High-Performance BiCMOS Transimpedance Amplifiers for Fiber-Optic Receivers

2007 ◽  
Vol 4 (1) ◽  
pp. 69
Author(s):  
F. Touati ◽  
M. Loulou
Keyword(s):  
Low Power ◽  
Detailed Analysis ◽  
Process Parameters ◽  
High Performance ◽  
Fiber Optic ◽  
High Gain ◽  
Low Noise ◽  
Transimpedance Amplifier ◽  
Transimpedance Amplifiers ◽  
Simulated Performance

High gain, wide bandwidth, low noise, and low-power transimpedance amplifiers based on new BiCMOS common- base topologies have been designed for fiber-optic receivers. In particular a design approach, hereafter called "A more- FET approach", added a new dimension to effectively optimize performance tradeoffs inherent in such circuits. Using conventional silicon 0.8 μm process parameters, simulated performance features of a total-FET transimpedance amplifier operating at 7.2 GHz, which is close to the technology fT of 12 GHz, are presented. The results are superior to those of similar recent designs and comparable to IC designs using GaAs technology. A detailed analysis of the design architecture, including a discussion on the effects of moving toward more FET-based designs is presented. 

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

A CMOS Low-Noise and Low-Power Transimpedance Amplifier

2021 ◽  
Author(s):  
Mehrdad Amirkhan Dehkordi ◽  
Seyed Mehdi Mirsanei ◽  
Soorena Zohoori
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Transimpedance Amplifier

scholarly journals 2.4 GHZ HETERODYNE RECEIVER FOR HEALTHCARE APPLICATION

2016 ◽  
Vol 8 (2) ◽  
pp. 22 ◽  
Author(s):  
Wei Cai ◽  
Frank Shi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Tuning Range ◽  
Low Noise ◽  
Heterodyne Receiver ◽  
The Third ◽  
Noise Amplifier ◽  
Lc Tank ◽  
Down Conversion

<p class="lead">The objective of this research was to design a basic 2.4 GHz heterodyne receiver for healthcare on a 130um CMOS process. The ultimate goal for the wireless industry is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. In the first part, a low noise amplifier (LNA), which is commonly used as the first stage of a receiver, is introduced and simulated. LNA performance greatly affects the overall receiver performance. The LNA was designed at the 2.4 GHz ISM band, using the cascode with an inductive degeneration topology. The second part of this thesis presents a low power 2.4 GHz down conversion Gilbert Cell mixer. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The design uses using PMOS cross-coupled topology with the varactor for wider tuning range topology. In the first part, a low noise amplifier (LNA) design reaches the NF of 2 dB, has a power consumption of 2.2 mW, and has a gain of 20dB. The second part of this proposal presents a low power 2.4 GHz down conversion Gilbert Cell mixer. The obtained result shows a conversion gain of 14.6 dB and power consumption of 8.2 mW at a 1.3V supply voltage. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The final simulation of the phase noise is-128 dBc/Hz, and the tuning range is 2.3 GHz-2.5 GHz while the total power consumption is 3.25 mW.<strong> </strong>The performance of the receiver meets the specification requirements of the desired standard.</p>

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

Sign in / Sign up

Export Citation Format

Share Document