ANALYSIS OF MODIFIED COSH WINDOW FUNCTION AND PERFORMANCE EVALUATION OF THE FIR FILTER DESIGNED USING WINDOWING TECHNIQUES

2012 ◽  
Vol 3 (2) ◽  
pp. 324-328
Author(s):  
Avinash Mehta ◽  
Munish Verma ◽  
Vijay K. Lamba ◽  
Susheel Kumar ◽  
Sandeep Kumar

Filters are used in electronic circuits to remove the unwanted frequency components from desired signals. A digital filter basically provide high attenuation to the unwanted ones and offer very low or ideally zero attenuation to desired signal components when it’s impulse response is adjusted as per requirement. For ideal filters, the length of such an impulse response is infinite and also the filter will be non-causal and unrealizable. So, we need to truncate this infinite impulse response to make it finite. For this truncation, we use window functions. Using window functions, we obtain a finite impulse response or simply FIR filter. The shape of a window in time domain decides the characteristics of resultant filter in frequency domain. Several window functions are available in literature. For the present work we have choosen the three parameter Cosh window for truncation of infinite impulse response. It is also called as modified Cosh window because it has been obtained by  inserting a third parameter in the basic 2-parameter Cosh window function. The main goal of this work is to study this modified Cosh window and design a digital low pass FIR filter using the same in MATLAB. First of all the properties of window function are described and frequeny domain responses of  window function is obtained. Then FIR filter is analyzed using window design method and it’s characteristics have also been studied in frequency domain.

2013 ◽  
Vol 333-335 ◽  
pp. 516-521
Author(s):  
Wei Zhou ◽  
Ti Jing Cai

There are a great number of high-frequency and low-frequency noises in the airborne gravity data, so the filtering technology is needed to pick up the weak gravity anomaly. Based on the current filtering methods in airborne gravity data processing: butterworth infinite impulse response(IIR) filtering, window function finite impulse response(FIR) filtering and Kalman smoothing, several methods were compared and studied for the measured airborne gravity data, and the accuracies of extracted gravity anomalies were presented. Results show that the accuracy of Kalman smoothing is better than that of the combined filtering with butterworth IIR and window function FIR.


2012 ◽  
Vol 3 (2) ◽  
pp. 329-334
Author(s):  
Susheel Kumar ◽  
Munish Verma ◽  
Vijay K. Lamba ◽  
Avinash Kumar ◽  
Sandeep Kumar

Filters are very commonly found in everyday life and include examples such as water filters for water purification, mosquito nets that filter out bugs, bouncers at bars filtering the incoming guests according to age (and other criteria), and air filters found in air conditioners that we are sometimes a bit too lazy to change/clean periodically. Filters have two uses: signal separation and signal restoration. Signal separation is needed when a signal has been contaminated with interference, noise, or other signals. For example, imagine a device for measuring the electrical activity of a baby's heart (EKG) while still in the womb. The raw signal will likely be corrupted by the breathing and heartbeat of the mother. A filter might be used to separate these signals so that they can be individually analyzed. Signal restoration is used when a signal has been distorted in some way. For example, an audio recording made with poor equipment may be filtered to better represent the sound as it actually occurred [1, 2]. The main goal of this work is to study the exponential  window function and analyze a digital low pass FIR filter using the same in MATLAB. Properties of window functions is studied and frequeny domain responses of  window functions is obtained. Then FIR filter is designed using widow design method and its characteristics have also been studied in frequency domain. The performace comparison between LPFs designed using other well known windows like Kaiser, Exponential, Cosh and modified kaiser window is done and it has been intuitively shown that for a given order and transition width, the filter designed using Exponential window provides the worse minimum stop band attenuation but better far end attenuation than filter designed by well known Kaiser Window.


2012 ◽  
Vol 239-240 ◽  
pp. 1194-1201
Author(s):  
Yan Guo ◽  
Shi Dan Li ◽  
De Sheng Wang

This paper presents an algorithm of sea clutter suppression using graphics processing unit (GPU) to meet the real-time requirement in the general radar terminal system. The main idea is to convert an infinite impulse response (IIR) filter to a finite impulse response (FIR) filter, which is suitable for the parallelization processing of GPU. Finally, the converted FIR filter algorithm is implemented on the GPU efficiently, achieving a speed approximately twice as fast as that of the previous IIR filter algorithm implemented on the CPU.


2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Mohan Kumar ◽  
Ranga Raju

Purpose Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization. Design/methodology/approach The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324. Findings The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively. Originality/value The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.


2014 ◽  
Vol 25 (1) ◽  
pp. 53-62
Author(s):  
Juan Camilo Valderrama-Cuervo ◽  
Alexander López-Parrado

This paper presents the design and implementation of three System-on-Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR-filter core is based on the symmetrical realization form, the IIRfilter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix 22 Single Delay Feedback (R22SDF) architecture. The three cores are compatible with the Wishbone SoC bus, and they were described using generic and structural VHDL. In-system hardware verification was performed by using an OpenRisc-based SoC synthesized on an Altera FPGA. Tests showed that the designed DSP cores are suitable for building SoC based on the OpenRisc processor and the Wishbone bus.


Author(s):  
Andrzej Handkiewicz ◽  
Mariusz Naumowicz

AbstractThe paper presents a method of optimizing frequency characteristics of filter banks in terms of their implementation in digital CMOS technologies in nanoscale. Usability of such filters is demonstrated by frequency-interleaved (FI) analog-to-digital converters (ADC). An analysis filter present in these converters was designed in switched-current technique. However, due to huge technological pitch of standard digital CMOS process in nanoscale, its characteristics substantially deviate from the required ones. NANO-studio environment presented in the paper allows adjustment, with transistor channel sizes as optimization parameters. The same environment is used at designing a digital synthesis filter, whereas optimization parameters are input and output conductances, gyration transconductances and capacitances of a prototype circuit. Transition between analog s and digital z domains is done by means of bilinear transformation. Assuming a lossless gyrator-capacitor (gC) multiport network as a prototype circuit, both for analysis and synthesis filter banks in FI ADC, is an implementation of the strategy to design filters with low sensitivity to parameter changes. An additional advantage is designing the synthesis filter as stable infinite impulse response (IIR) instead of commonly used finite impulse response (FIR) filters. It provides several dozen-fold saving in the number of applied multipliers.. The analysis and synthesis filters in FI ADC are implemented as filter pairs. An additional example of three-filter bank demonstrates versatility of NANO-studio software.


2016 ◽  
Vol 24 (6) ◽  
pp. 1086-1100
Author(s):  
Utku Boz ◽  
Ipek Basdogan

In adaptive control applications for noise and vibration, finite ımpulse response (FIR) or ınfinite ımpulse response (IIR) filter structures are used for online adaptation of the controller parameters. IIR filters offer the advantage of representing dynamics of the controller with smaller number of filter parameters than with FIR filters. However, the possibility of instability and convergence to suboptimal solutions are the main drawbacks of such controllers. An IIR filtering-based Steiglitz–McBride (SM) algorithm offers nearly-optimal solutions. However, real-time implementation of the SM algorithm has never been explored and application of the algorithm is limited to numerical studies for active vibration control. Furthermore, the prefiltering procedure of the SM increases the computational complexity of the algorithm in comparison to other IIR filtering-based algorithms. Based on the lack of studies about the SM in the literature, an SM time-domain algorithm for AVC was implemented both numerically and experimentally in this study. A methodology that integrates frequency domain IIR filtering techniques with the classic SM time-domain algorithm is proposed to decrease the computational complexity. Results of the proposed approach are compared with the classical SM algorithm. Both SM and the proposed approach offer multimodal vibration suppression and it is possible to predict the performance of the controller via simulations. The proposed hybrid approach ensures similar vibration suppression performance compared to the classical SM and offers computational advantage as the number of control filter parameters increases.


Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.


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