Synthesis method of high speed finite state machines

2010 ◽  
Vol 58 (4) ◽  
pp. 635-644 ◽  
Author(s):  
R. Czerwiński ◽  
D. Kania

Synthesis method of high speed finite state machines The paper is concerned with the problem of state assignment and logic optimization of high speed finite state machines. The method is designed for PAL-based CPLDs implementations. Determining the number of logic levels of the transition function before the state encoding process, and keeping the constraints during the process is the main problem at hand. A number of coding bits, as well as codes for the states, are adjusted to achieve a machine with a determined number of logic levels. Elements of two-level minimization are taken into consideration in the state assignment. The proposed optimization method is based on utilizing tri-state buffers, thus enabling achievement of a one-logic-level output block.

VLSI Design ◽  
1994 ◽  
Vol 2 (2) ◽  
pp. 105-116
Author(s):  
S. Muddappa ◽  
R. Z. Makki ◽  
Z. Michalewicz ◽  
S. Isukapalli

In this paper we present a new tool for the encoding of multi-level finite state machines based on the concept of evolution programming. Evolution programs are stochastic adaptive algorithms, based on the paradigm of genetic algorithms whose search methods model some natural phenomenon: genetic inheritance and Darwinian strife for survival. Crossover and mutation rates were tailored to the state assignment problem experimentally. We present results over a wide range of MCNC benchmarks which demonstrate the effectiveness of the new tool. The results show that evolution programs can be effectively applied to state assignment.


1994 ◽  
Vol 30 (8) ◽  
pp. 627-629 ◽  
Author(s):  
S.K. Hong ◽  
I.C. Park ◽  
C.M. Kyung ◽  
S.H. Hwang

2015 ◽  
Vol 24 (07) ◽  
pp. 1550101 ◽  
Author(s):  
Raouf Senhadji-Navaro ◽  
Ignacio Garcia-Vargas

This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-based reconfigurable multiplexer bank, VRMUX). The performance (in terms of speed, area and reconfiguration cost) of both architectures is compared. Experimental results from MCNC finite state machine (FSM) benchmarks show that CRMUX is faster and more area-efficient than VRMUX. The reconfiguration cost of both multiplexer banks is studied using a behavioral model of a reconfigurable state machine. The results show that the reconfiguration cost of CRMUX is lower than that of VRMUX in most cases.


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