scholarly journals Comparative analysis of matching pursuit algorithms for Kirchhoff migration on compressed data

2021 ◽  
Vol 11 (1) ◽  
pp. 47-53
Author(s):  
Carlos A. Fajardo ◽  
Fabián Sánchez ◽  
Ana B. Ramirez
Keyword(s):  
Matching Pursuit ◽  
Main Memory ◽  
Memory Access ◽  
Seismic Survey ◽  
Kirchhoff Migration ◽  
Recorded Data ◽  
Memory Accesses ◽  
Mathematical Operations ◽  
Compressed Data ◽  
Disk Memory

Currently, the amount of recorded data in a seismic survey is in the order of hundreds of Terabytes. The processing of such amount of data implies significant computational challenges. One of them is the I/O bottleneck between the main memory and the node memory. This bottleneck results from the fact that the disk memory access speed is thousands-fold slower than the processing speed of the co-processors (eg. GPUs). We propose a special Kirchhoff migration that develops the migration process over compressed data. The seismic data is compressed by using three well-known Matching Pursuit algorithms. Our approach seeks to reduce the number of memory accesses to the disk required by the Kirchhoff operator and to add more mathematical operations to the traditional Kirchhoff migration. Thus, we change slow operations (memory access) for fast operations (math operations). Experimental results show that the proposed method preserves, to a large extent, the seismic attributes of the image for a compression ratio up to 20:1.

scholarly journals Online Thread and Data Mapping Using a Sharing-Aware Memory Management Unit

2021 ◽  
Vol 5 (4) ◽  
pp. 1-28
Author(s):  
Eduardo H. M. Cruz ◽  
Matthias Diener ◽  
Laércio L. Pilla ◽  
Philippe O. A. Navaux
Keyword(s):  
Energy Efficiency ◽  
Memory Management ◽  
Substantial Reduction ◽  
Management Unit ◽  
Memory Access ◽  
Parallel Applications ◽  
Data Mapping ◽  
Wide Range ◽  
Memory Accesses ◽  
Level Parallelism

Current and future architectures rely on thread-level parallelism to sustain performance growth. These architectures have introduced a complex memory hierarchy, consisting of several cores organized hierarchically with multiple cache levels and NUMA nodes. These memory hierarchies can have an impact on the performance and energy efficiency of parallel applications as the importance of memory access locality is increased. In order to improve locality, the analysis of the memory access behavior of parallel applications is critical for mapping threads and data. Nevertheless, most previous work relies on indirect information about the memory accesses, or does not combine thread and data mapping, resulting in less accurate mappings. In this paper, we propose the Sharing-Aware Memory Management Unit (SAMMU), an extension to the memory management unit that allows it to detect the memory access behavior in hardware. With this information, the operating system can perform online mapping without any previous knowledge about the behavior of the application. In the evaluation with a wide range of parallel applications (NAS Parallel Benchmarks and PARSEC Benchmark Suite), performance was improved by up to 35.7% (10.0% on average) and energy efficiency was improved by up to 11.9% (4.1% on average). These improvements happened due to a substantial reduction of cache misses and interconnection traffic.

Study and Optimization of T-Tree Index in Main Memory Database

2013 ◽  
Vol 427-429 ◽  
pp. 2531-2535 ◽  
Author(s):  
Feng Dong Sun ◽  
Quan Guo ◽  
Lan Wang
Keyword(s):  
High Performance ◽  
Main Memory ◽  
Memory Access ◽  
Index Structure ◽  
Index Structures ◽  
Clock Speed ◽  
Main Memory Database ◽  
Tree Index ◽  
Overall Performance

The bottleneck is not the disk I/O but CUP clock speed faster than the memory speed in main memory database .In order to achieve high performance in main memory database ,it is a good approach to design new index structures to improve the memory access speed .This chapter presents a T-tree index structure and its algorithms in main memory database firstly .Then presents two results on Optimization of T-tree index ,including T-tail tree and TTB-tree. Our results indicate that the T-Tree provides good overall performance in main memory.

scholarly journals Searching using B/B+ Tree in Database Management System

2021 ◽  
Vol 9 (VII) ◽  
pp. 3702-3706
Author(s):  
Anshita Garg
Keyword(s):  
Data Transfer ◽  
Main Memory ◽  
Database Management System ◽  
Memory Access ◽  
Space Complexity ◽  
Longest Common Subsequence ◽  
Time And Space ◽  
Basic Point ◽  
Disk Access ◽  
Time And Space Complexity

This is a research-based project and the basic point motivating this project is learning and implementing algorithms that reduce time and space complexity. In the first part of the project, we reduce the time taken to search a given record by using a B/B+ tree rather than indexing and traditional sequential access. It is concluded that disk-access times are much slower than main memory access times. Typical seek times and rotational delays are of the order of 5 to 6 milliseconds and typical data transfer rates are of the range of 5 to 10 million bytes per second and therefore, main memory access times are likely to be at least 4 or 5 orders of magnitude faster than disk access on any given system. Therefore, the objective is to minimize the number of disk accesses, and thus, this project is concerned with techniques for achieving that objective i.e. techniques for arranging the data on a disk so that any required piece of data, say some specific record, can be located in a few I/O’s as possible. In the second part of the project, Dynamic Programming problems were solved with Recursion, Recursion With Storage, Iteration with Storage, Iteration with Smaller Storage. The problems which have been solved in these 4 variations are Fibonacci, Count Maze Path, Count Board Path, and Longest Common Subsequence. All 4 variations are an improvement over one another and thus time and space complexity are reduced significantly as we go from Recursion to Iteration with Smaller Storage.

scholarly journals ASIC Implementation of DMA Controller

2016 ◽  
Vol 4 (1) ◽  
pp. 1-4
Author(s):  
Aman Agarwal ◽  
Arjun J Anil ◽  
Rahul Nair ◽  
K. Sivasankaran
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
System Performance ◽  
Direct Memory Access ◽  
Main Memory ◽  
Memory Access ◽  
Verilog Hdl ◽  
Peripheral Device ◽  
Power Constraints ◽  
System Memory

Direct Memory Access is a method of transferring data between peripherals and memory without using the CPU. It is designed to improve system performance by allowing external devices to directly transfer information from the system memory. We generally use asynchronous type of DMA as they respond directly to input. The DMA controller issues signals to the peripheral device and main memory to execute read and write commands. In this paper DMA controller was designed using Verilog HDL and simulated in Cadence NC Launch. The design was synthesized using low power constraints. Through this design we have decreased the power consumption to 69%.

Heterogeneity-aware Multicore Synchronization for Intermittent Systems

2021 ◽  
Vol 20 (5s) ◽  
pp. 1-22
Author(s):  
Wei-Ming Chen ◽  
Tei-Wei Kuo ◽  
Pi-Cheng Hsiu
Keyword(s):  
Energy Harvesting ◽  
Memory Access ◽  
Experimental Results ◽  
Data Consistency ◽  
Adaptive Synchronization ◽  
Power Cycles ◽  
Cpu Time ◽  
Multiple Cores ◽  
Non Volatile Memory ◽  
Memory Accesses

Intermittent systems enable batteryless devices to operate through energy harvesting by leveraging the complementary characteristics of volatile (VM) and non-volatile memory (NVM). Unfortunately, alternate and frequent accesses to heterogeneous memories for accumulative execution across power cycles can significantly hinder computation progress. The progress impediment is mainly due to more CPU time being wasted for slow NVM accesses than for fast VM accesses. This paper explores how to leverage heterogeneous cores to mitigate the progress impediment caused by heterogeneous memories. In particular, a delegable and adaptive synchronization protocol is proposed to allow memory accesses to be delegated between cores and to dynamically adapt to diverse memory access latency. Moreover, our design guarantees task serializability across multiple cores and maintains data consistency despite frequent power failures. We integrated our design into FreeRTOS running on a Cypress device featuring heterogeneous dual cores and hybrid memories. Experimental results show that, compared to recent approaches that assume single-core intermittent systems, our design can improve computation progress at least 1.8x and even up to 33.9x by leveraging core heterogeneity.

scholarly journals Memory Access Behavior Analysis of NUMA-Based Shared Memory Programs

2002 ◽  
Vol 10 (1) ◽  
pp. 45-53 ◽  
Author(s):  
Jie Tao ◽  
Wolfgang Karl ◽  
Martin Schulz
Keyword(s):  
Shared Memory ◽  
Data Locality ◽  
Memory Access ◽  
Remote Memory ◽  
Data Layout ◽  
Performance Improvements ◽  
Significant Performance ◽  
Working Set ◽  
Memory Accesses ◽  
Memory Applications

Shared memory applications running transparently on top of NUMA architectures often face severe performance problems due to bad data locality and excessive remote memory accesses. Optimizations with respect to data locality are therefore necessary, but require a fundamental understanding of an application's memory access behavior. The information necessary for this cannot be obtained using simple code instrumentation due to the implicit nature of the communication handled by the NUMA hardware, the large amount of traffic produced at runtime, and the fine access granularity in shared memory codes. In this paper an approach to overcome these problems and thereby to enable an easy and efficient optimization process is presented. Based on a low-level hardware monitoring facility in coordination with a comprehensive visualization tool, it enables the generation of memory access histograms capable of showing all memory accesses across the complete address space of an application's working set. This information can be used to identify access hot spots, to understand the dynamic behavior of shared memory applications, and to optimize applications using an application specific data layout resulting in significant performance improvements.

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