scholarly journals ASIC Implementation of DMA Controller

2016 ◽  
Vol 4 (1) ◽  
pp. 1-4
Author(s):  
Aman Agarwal ◽  
Arjun J Anil ◽  
Rahul Nair ◽  
K. Sivasankaran
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
System Performance ◽  
Direct Memory Access ◽  
Main Memory ◽  
Memory Access ◽  
Verilog Hdl ◽  
Peripheral Device ◽  
Power Constraints ◽  
System Memory

Direct Memory Access is a method of transferring data between peripherals and memory without using the CPU. It is designed to improve system performance by allowing external devices to directly transfer information from the system memory. We generally use asynchronous type of DMA as they respond directly to input. The DMA controller issues signals to the peripheral device and main memory to execute read and write commands. In this paper DMA controller was designed using Verilog HDL and simulated in Cadence NC Launch. The design was synthesized using low power constraints. Through this design we have decreased the power consumption to 69%.

INFLUENCE OF INPUT/OUTPUT OPERATIONS ON PROCESSOR PERFORMANCE

2006 ◽  
Vol 15 (01) ◽  
pp. 43-56
Author(s):  
JOSE MARIA RODRÍGUEZ CORRAL ◽  
ANTON CIVIT BALCELLS ◽  
GABRIEL JIMENEZ MORENO ◽  
JOSE LUIS SEVILLANO RAMOS ◽  
ARTURO MORGADO ESTEVEZ
Keyword(s):  
High Speed ◽  
Discrete Event ◽  
Direct Memory Access ◽  
Main Memory ◽  
Digital Cameras ◽  
Video Capture ◽  
Negative Effects ◽  
Processor Performance ◽  
System Memory ◽  
Computer Processor

Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, …). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I/O scenarios where the peripherals operate. This software has been used to analyze the performance of four different processors in four I/O scenarios: video capture, video capture and playback, high speed network, and serial transmission.

scholarly journals Low Power 11T Adder Comparator Design

2020 ◽  
Vol 9 (1) ◽  
pp. 28
Author(s):  
C.M.R. Prabhu ◽  
Tan Wee Xin Wilson ◽  
T. Bhuvaneswari
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
System Performance ◽  
Power Loss ◽  
Digital System ◽  
Basic Block ◽  
Top Down ◽  
Higher Temperature ◽  
Processor Unit ◽  
Main Components

Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.

scholarly journals A Delay-Based Machine Learning Model for DMA Attack Mitigation

Cryptography ◽  
2021 ◽  
Vol 5 (3) ◽  
pp. 18
Author(s):  
Yutian Gui ◽  
Chaitanya Bhure ◽  
Marcus Hughes ◽  
Fareena Saqib
Keyword(s):  
Machine Learning ◽  
Direct Memory Access ◽  
Main Memory ◽  
Memory Access ◽  
Unique Identifier ◽  
Device Identification ◽  
Processing Power ◽  
Host Machine ◽  
Minimal Modification ◽  
Time Required

Direct Memory Access (DMA) is a state-of-the-art technique to optimize the speed of memory access and to efficiently use processing power during data transfers between the main system and a peripheral device. However, this advanced feature opens security vulnerabilities of access compromise and to manipulate the main memory of the victim host machine. The paper outlines a lightweight process that creates resilience against DMA attacks minimal modification to the configuration of the DMA protocol. The proposed scheme performs device identification of the trusted PCIe devices that have DMA capabilities and constructs a database of profiling time to authenticate the trusted devices before they can access the system. The results show that the proposed scheme generates a unique identifier for trusted devices and authenticates the devices. Furthermore, a machine learning–based real-time authentication scheme is proposed that enables runtime authentication and share the results of the time required for training and respective accuracy.

scholarly journals RDMA Communciation Patterns

2020 ◽  
Vol 20 (3) ◽  
pp. 199-210
Author(s):  
Tobias Ziegler ◽  
Viktor Leis ◽  
Carsten Binnig
Keyword(s):  
Systematic Study ◽  
Direct Memory Access ◽  
Communication Patterns ◽  
Main Memory ◽  
Memory Access ◽  
Performance Characteristics ◽  
Low Latency ◽  
Hard Problem ◽  
High Bandwidth

Abstract Remote Direct Memory Access (RDMA) is a networking protocol that provides high bandwidth and low latency accesses to a remote node’s main memory. Although there has been much work around RDMA, such as building libraries on top of RDMA or even applications leveraging RDMA, it remains a hard problem to identify the most suitable RDMA primitives and their combination for a given problem. While there have been some initial studies included in papers that aim to investigate selected performance characteristics of particular design choices, there has not been a systematic study to evaluate the communication patterns of scale-out systems. In this paper, we address this issue by systematically investigating how to efficiently use RDMA for building scale-out systems.

scholarly journals Low Power Adder Based Digital Filter for QRS Detector

2014 ◽  
Vol 2014 ◽  
pp. 1-5
Author(s):  
L. Murali ◽  
D. Chitra ◽  
T. Manigandan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Filter ◽  
Full Adder ◽  
Leakage Power ◽  
System Level ◽  
Complex Signal ◽  
Verilog Hdl ◽  
Processing Elements ◽  
Signal Processors

Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.

Optimal design of a high homogeneous and small-size shim coil for atomic spin gyroscope based on 0-1 linear programming

2020 ◽  
Vol 64 (1-4) ◽  
pp. 165-172
Author(s):  
Dongge Deng ◽  
Mingzhi Zhu ◽  
Qiang Shu ◽  
Baoxu Wang ◽  
Fei Yang
Keyword(s):  
Linear Programming ◽  
Power Consumption ◽  
Low Power ◽  
Optimization Design ◽  
Structural Parameters ◽  
Axial Position ◽  
Low Power Consumption ◽  
Optimal Method ◽  
Atomic Spin ◽  
Shim Coil

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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