Advanced Optical Testing of an Array in 65 nm CMOS Technology
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Abstract In this paper we present the advanced optical testing of an array fabricated in IBM’s 65 nm SOI CMOS technology, using the Picosecond Imaging Circuit Analysis (PICA) [1-11] tool equipped with the Superconducting Single-Photon Detector (SSPD) [12,13]. Based on the results of the optical analysis we were able to confirm a time collision problem in the readout circuit of the array. In the following sections we will also discuss the use of an innovative optical packaging for testing chips requiring wire-bonding, along with record low voltage optical measurements, down to 0.7 V.
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2013 ◽
Vol 201
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pp. 342-351
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2018 ◽
Vol 89
(6)
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pp. 063117
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2004 ◽
Vol 44
(9-11)
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pp. 1663-1668
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