An Application of a Nanoprobe Technique in the Characterization of Advanced SRAM Devices

2008 ◽  
Author(s):  
Hung-Sung Lin ◽  
Chun-Ming Chen
Keyword(s):  
Barrier Layer ◽  
Gate Oxide ◽  
Active Area ◽  
Technology Node ◽  
Channel Gate ◽  
Oxide Defects ◽  
Contact Barrier

Abstract The importance of understanding mismatched behavior in SRAM devices has increased as the technology node has shrunk below 100nm. Using the nanoprobe technique [1-3], the MOS characteristics of failure bits in actual SRAM cells have been directly measured. After transistors that are failing were identified, the best approach for identifying nanoscale defects was determined. In this study, several types of nanoscale defects, such as offset spacer residue, salicide missing from the active area, doping missing from the channel, gate oxide defects, contact barrier layer residue, and severed poly-gate silicide were successfully discovered.

Physical Failure Analysis Techniques for Front-End-of-Line Defect Analysis

2016 ◽  
Author(s):  
Dirk Doyle ◽  
Lawrence Benedict ◽  
Fritz Christian Awitan
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Gate Oxide ◽  
Top Down ◽  
New Techniques ◽  
First Case ◽  
Transmission Electron ◽  
Scanning Transmission

Abstract Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.

Characterization of leakage current in thin gate oxide subjected to 10 keV X-ray irradiation

2000 ◽  
Vol 47 (3) ◽  
pp. 650-652 ◽  
Author(s):  
C.H. Ling ◽  
C.H. Ang ◽  
D.S. Ang
Keyword(s):  
Leakage Current ◽  
Gate Oxide ◽  
X Ray ◽  
Thin Gate Oxide

Octahedral-Structured Gigantic Precipitates as the Origin of Gate-Oxide Defects in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 812-817 ◽  
Author(s):  
Manabu Itsumi ◽  
Hideo Akiya ◽  
Takemi Ueki ◽  
Masato Tomita ◽  
Masataka Yamawaki
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Large Scale ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Oxide Defects

Characterization of Ba-Introduced Thin Gate Oxide on 4H-SiC

2019 ◽  
Vol 963 ◽  
pp. 451-455 ◽  
Author(s):  
Kosuke Muraoka ◽  
Seiji Ishikawa ◽  
Hiroshi Sezaki ◽  
Tomonori Maeda ◽  
Shinichiro Kuroki
Keyword(s):  
Oxygen Concentration ◽  
Barrier Layer ◽  
Gate Oxide ◽  
Interface State ◽  
State Density ◽  
Conduction Band Edge ◽  
Low Oxygen ◽  
Barrier Layer Thickness ◽  
Thick Barrier ◽  
Thin Gate Oxide

A thickness of Ba-introduced gate oxide was controlled with the oxygen concentration and a barrier layer thickness at a post-deposition annealing. The oxidation rate becomes slower with the low oxygen concentration and the thick barrier layer, and the thin oxide of 12 nm was realized with O2 5% and 9 nm of the barrier layer. This Ba-introduced thin gate oxide resulted in the field effect mobility of 13 cm2/Vs and the interface state density of 2×1011 cm-2eV-1 at 0.25 eV below the conduction band edge of 4H-SiC.

Characteristics of ALD Tungsten Nitride Using B2H6, WF6, and NH3 and Application to Contact Barrier Layer for DRAM

2007 ◽  
Vol 154 (8) ◽  
pp. D435 ◽  
Author(s):  
Soo-Hyun Kim ◽  
Jun-Ki Kim ◽  
Ju Hee Lee ◽  
Nohjung Kwak ◽  
Jinwoong Kim ◽  
...  
Keyword(s):  
Barrier Layer ◽  
Tungsten Nitride ◽  
Contact Barrier

Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry

2018 ◽  
Vol 924 ◽  
pp. 697-702 ◽  
Author(s):  
Sauvik Chowdhury ◽  
Levi Gant ◽  
Blake Powell ◽  
Kasturirangan Rangaswamy ◽  
Kevin Matocha
Keyword(s):  
Room Temperature ◽  
Stress Testing ◽  
Short Circuit ◽  
Gate Oxide ◽  
High Volume ◽  
Inductive Load ◽  
Switching Losses ◽  
Oxide Reliability ◽  
Silicon Cmos

This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.

Growth and characterization of AlGaN/GaN heterostructure using unintentionally doped AlN/GaN superlattices as barrier layer

2009 ◽  
Vol 45 (2) ◽  
pp. 54-59 ◽  
Author(s):  
M.L. Zhang ◽  
X.L. Wang ◽  
H.L. Xiao ◽  
C.M. Wang ◽  
C.B. Yang ◽  
...  
Keyword(s):  
Barrier Layer ◽  
Gan Heterostructure
Sign in / Sign up

Export Citation Format

Share Document