Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry

2018 ◽  
Vol 924 ◽  
pp. 697-702 ◽  
Author(s):  
Sauvik Chowdhury ◽  
Levi Gant ◽  
Blake Powell ◽  
Kasturirangan Rangaswamy ◽  
Kevin Matocha
Keyword(s):  
Room Temperature ◽  
Stress Testing ◽  
Short Circuit ◽  
Gate Oxide ◽  
High Volume ◽  
Inductive Load ◽  
Switching Losses ◽  
Oxide Reliability ◽  
Silicon Cmos

This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.

Superior Short Circuit Performance of 1.2kV SiC JBSFETs Compared to 1.2kV SiC MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 797-800 ◽  
Author(s):  
Ajit Kanale ◽  
Ki Jeong Han ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya
Keyword(s):  
High Temperature ◽  
Short Circuit ◽  
Switching Loss ◽  
Switching Circuit ◽  
Inductive Load ◽  
Circuit Performance ◽  
Switching Performance ◽  
Turn On ◽  
Switching Losses ◽  
High Side

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.

Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

2020 ◽  
Vol 1004 ◽  
pp. 770-775
Author(s):  
Rina Tanaka ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
Hideyuki Hatta ◽  
Hidenori Koketsu ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Short Circuit ◽  
Effective Means ◽  
Gate Oxide ◽  
Device Performance ◽  
High Concentration ◽  
Safe Operation ◽  
Major Drawback ◽  
Oxide Reliability ◽  
Conventional Device

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.

TXRF Characterization of Trace Metal Contamination in Thin Gate Oxides

1992 ◽  
Vol 259 ◽  
Author(s):  
R. S. Hockett ◽  
Diane Hymes
Keyword(s):  
Metal Contamination ◽  
Gate Oxide ◽  
Silicon Substrates ◽  
Qualitative Information ◽  
Gate Oxides ◽  
Quantitative Estimates ◽  
Oxide Reliability ◽  
First Time ◽  
Non Destructive

ABSTRACTMetal contamination on the surface of silicon substrates before gate oxidation is known to affect gate oxide reliability. For the first time this study presents a non-destructive, analytical measurement of transition metals in an 8nm gate oxide grown by a 920 °C-10min-dry oxidation of an intentionally contaminated silicon surface. The TECHNOS TREX 610 TXRF anglescan of the gate oxide provides qualitative information on the location of the metals. The data indicate the Fe is on or in the oxide, the Cu is below the oxide, the Zn is on the oxide, and the Ni may be both in the oxide and below the oxide layer. In addition, quantitative estimates from the TXRF data indicate that all the original Fe and Cu are present, while only portions of Zn and Ni are detected after the oxidation.

600 V -Class V-Groove SiC MOSFETs

2014 ◽  
Vol 778-780 ◽  
pp. 931-934 ◽  
Author(s):  
Yu Saitoh ◽  
Masaki Furumai ◽  
Toru Hiyoshi ◽  
Keiji Wada ◽  
Takeyoshi Masuda ◽  
...  
Keyword(s):  
Low Temperature ◽  
Oxide Layer ◽  
Room Temperature ◽  
Gate Oxide ◽  
Class V ◽  
Turn On ◽  
Switching Losses ◽  
Thick Oxide Layer ◽  
Switching Characteristics ◽  
Off Time

The authors applied a thick gate oxide layer at the trench bottoms to 600 V class truncated V-groove MOSFETs of which MOS channels were formed on 4H-SiC (0-33-8) facets and validated the static and switching characteristics. The specific on-resistance and the threshold voltage were 3.6 mΩ cm2(VGS=18 V,VDS=1 V) and about 1 V (normally-off), respectively. The breakdown voltage of the MOSFET with a thick oxide layer was 1,125 V (IDS=1 μA). The switching losses during turn-on and turn-off operations were estimated to be 105.8 μJ and 82.5 μJ (300 V, 10 A) at room temperature. The switching characteristics exhibited low temperature dependence for turn-on/off time.

Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices

2007 ◽  
Vol 46 (11) ◽  
pp. 7256-7262 ◽  
Author(s):  
Min Gyu Sung ◽  
Kwan-Yong Lim ◽  
Heung-Jae Cho ◽  
Seung Ryong Lee ◽  
Se-Aug Jang ◽  
...  
Keyword(s):  
Diffusion Barrier ◽  
Gate Oxide ◽  
Memory Devices ◽  
Oxide Reliability

3300V SiC DMOSFETs Fabricated in High-Volume 150 mm CMOS Fab

2018 ◽  
Vol 924 ◽  
pp. 731-734 ◽  
Author(s):  
Blake Powell ◽  
Kevin Matocha ◽  
Sauvik Chowdhury ◽  
Chris Hundley
Keyword(s):  
Silicon Carbide ◽  
Electric Fields ◽  
Room Temperature ◽  
Gate Oxide ◽  
High Volume ◽  
Optimized Design

We fabricated 3300V Silicon Carbide (SiC) DMOSFETs on 150mm substrates in a high volume automotive qualified Si CMOS foundry. In this paper we will show that JFET optimization can yield noticeable improvements in on-state performance without exceeding acceptable gate oxide electric fields. For the optimized design, breakdown voltages (BV) in excess of 3900V are observed along with a specific on resistance of 13.5mOhm-cm2 at room temperature and 30mOhm-cm2 at 150°C.

Gate Oxide Reliability Issues of SiC MOSFETs Under Short-Circuit Operation

2015 ◽  
Vol 30 (5) ◽  
pp. 2445-2455 ◽  
Author(s):  
Thanh-That Nguyen ◽  
Ashraf Ahmed ◽  
T. V. Thang ◽  
Joung-Hu Park
Keyword(s):  
Short Circuit ◽  
Gate Oxide ◽  
Oxide Reliability

Gate Oxide Reliability of 4H-SiC V-Groove Trench MOSFET with Thick Bottom Oxide

2015 ◽  
Vol 821-823 ◽  
pp. 741-744
Author(s):  
Toru Hiyoshi ◽  
Takeyoshi Masuda ◽  
Yu Saitoh ◽  
Keiji Wada ◽  
Takashi Tsuno ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Oxide ◽  
The Novel ◽  
Constant Voltage ◽  
Channel Mobility ◽  
Oxide Reliability ◽  
Blocking Voltage ◽  
Voltage Stress ◽  
The Stability

The authors reported the DMOSFETs fabricated on the 4H-SiC(0-33-8) in ECSCRM2012 and the novel V-groove MOSFETs, having (0-33-8) on the trench sidewall in ICSCRM2013. In this paper, we applied both the thick bottom oxide and the buried p+ regions to the V-groove MOSFETs for the protection of the trench bottom oxide. The V-groove MOSFET showed the low specific on-resistance of 3.2 mΩcm2 and the high blocking voltage of 1700 V on the bounty of the high channel mobility and the gate oxide protection, respectively. We also tested the gate oxide reliability of the V-groove MOSFET by constant-voltage stress TDDB measurement. The charge-to-breakdown was 18.0 C/cm2 at room temperature and 4.4 C/cm2 at 145°C. In addition, the stability of the threshold voltage was characterized with the VMOSFETs.

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