scholarly journals SIMULATION OF PARASITIC TUNNEL CURRENTS IN FLASH-MEMORY ELEMENTS BASED ON SHORT-CHANNEL MOS-TRANSISTORS

2020 ◽  
Vol 2 (7(76)) ◽  
pp. 26-28
Author(s):  
Oleg Grygoryevich Zhevnyak
Keyword(s):  
Flash Memory ◽  
Tunneling Current ◽  
Floating Gate ◽  
Memory Cells ◽  
Mos Transistors ◽  
Short Channel ◽  
Drain Bias ◽  
Parasitic Currents ◽  
Information Regime ◽  
Long Storage

Simulation of parasitic currents in Flash-memory cells based on short-channel MOSFET. In present paper the distributions of parasitic tunneling current as well as mean electron energy and mobility along the channel are calculated for short-channel MOSFETs by using Monte Carlo simulation of electron drift in such devices. The effect of drain bias in Flash-memory cells on these distributions is investigated for reading information regime. It is shown that the value of parasitic current is very small at considered conditions. But long storage can be change the charge in a floating gate of short-channel MOSFETs.

CARBON NANOTUBE BASED NONVOLATILE MEMORY DEVICES

2006 ◽  
Vol 16 (04) ◽  
pp. 959-975 ◽  
Author(s):  
YUEGANG ZHANG
Keyword(s):  
Carbon Nanotube ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Memory Performance ◽  
Memory Device ◽  
Floating Gate ◽  
Memory Devices ◽  
Memory Cells ◽  
Nonvolatile Memory Devices ◽  
Electrostatic Coupling

The technology progress and increasing high density demand have driven the nonvolatile memory devices into nanometer scale region. There is an urgent need of new materials to address the high programming voltage and current leakage problems in the current flash memory devices. As one of the most important nanomaterials with excellent mechanical and electronic properties, carbon nanotube has been explored for various nonvolatile memory applications. While earlier proposals of "bucky shuttle" memories and nanoelectromechanical memories remain as concepts due to fabrication difficulty, recent studies have experimentally demonstrated various prototypes of nonvolatile memory cells based on nanotube field-effect-transistor and discrete charge storage bits, which include nano-floating gate memory cells using metal nanocrystals, oxide-nitride-oxide memory stack, and more simpler trap-in-oxide memory devices. Despite of the very limited research results, distinct advantages of high charging efficiency at low operation voltage has been demonstrated. Single-electron charging effect has been observed in the nanotube memory device with quantum dot floating gates. The good memory performance even with primitive memory cells is attributed to the excellent electrostatic coupling of the unique one-dimensional nanotube channel with the floating gate and the control gate, which gives extraordinary charge sensibility and high current injection efficiency. Further improvement is expected on the retention time at room temperature and programming speed if the most advanced fabrication technology were used to make the nanotube based memory cells.

Overview of Advanced 3D Charge-trapping Flash Memory Devices

2010 ◽  
Vol 1250 ◽  
Author(s):  
Hang-Ting Lue ◽  
Kuang-Yeu Hsieh ◽  
Chih-Yuan Lu
Keyword(s):  
Flash Memory ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Floating Gate ◽  
Statistical Fluctuation ◽  
Silicon Thin Film ◽  
Short Channel ◽  
Channel Effect ◽  
Memory Architectures ◽  
3D Memory

AbstractAlthough conventional floating gate (FG) Flash memory has already gone into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges include FG interference, few-electron storage caused statistical fluctuation, poor short-channel effect, WL-WL breakdown, poor reliability, and edge effect sensitivity. Although charge-trapping (CT) devices have been proposed very early and studied for many years, these devices have not prevailed over FG Flash in the > 30nm node. However, beyond 20nm the advantage of CT devices may become more significant. Especially, due to the simpler structure and no need for charge storage isolation, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the Moore's law to continue for at least another decade. In this paper, we review the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss 3D memory architectures including the bit-cost scalable approach. Technology challenges and the poly-silicon thin film transistor (TFT) issues will be addressed in detail.

Characterizing Gate Disturb Embedded Flash Memory Cells by Atomic Force Probing

2010 ◽  
Author(s):  
M. Hoffmann ◽  
C. Nowak ◽  
A. Haase ◽  
S. Eckl
Keyword(s):  
Flash Memory ◽  
Failure Mechanisms ◽  
Floating Gate ◽  
Hot Electrons ◽  
Memory Cells ◽  
Main Root ◽  
Atomic Force ◽  
Test Algorithm ◽  
Embedded Flash

Abstract There are two known failure mechanisms that cause Gate Disturb failures in flash devices. One main electrically classified failure is the Gate Disturb failure. A second mechanism is the Floating Gate charging caused by high energetic electrons, so-called channel hot electrons, jumping above the energetic barrier of tunnel oxide. This paper describes the characterization of a single transistor Flash cell with the nano-probing approach and introduces a test algorithm to distinguish between these mechanisms at a Gate Disturb affected Flash cell. A Keithley parameter analyzer in combination with Atomic Force Probing (AFP) has been used for the Flash cell device characterization. A Gate Disturb defect can be induced by different defect mechanisms. Two of them, TRAP's in tunnel oxide and channel hot electrons as a result of leaky PN-junctions, were identified as the main root causes. These mechanisms can be distinguished by AFP-analysis with the tests presented in the paper.

First Detection of Single-Electron Charging of the Floating Gate of NAND Flash Memory Cells

2015 ◽  
Vol 36 (2) ◽  
pp. 132-134 ◽  
Author(s):  
Christian Monzio Compagnoni ◽  
Giovanni M. Paolucci ◽  
Carmine Miccoli ◽  
Alessandro S. Spinelli ◽  
Andrea L. Lacaita ◽  
...  
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Single Electron ◽  
Memory Cells ◽  
Nand Flash ◽  
Nand Flash Memory

Floating-Gate Corner-Enhanced Poly-to-Poly Tunneling in Split-Gate Flash Memory Cells

2012 ◽  
Vol 59 (1) ◽  
pp. 5-11 ◽  
Author(s):  
Yuri Tkachev ◽  
Xian Liu ◽  
Alexander Kotov
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Memory Cells
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