Environment for the analysis of functional self-test quality in digital systems

FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, testing of them is one of the major challenges for designers. Among various test methods, the Built-in Self-Test (BIST) based ones have shown good performance. In this paper, we presented a BIST-based approach to test LUTs as most vulnerable part of FPGA chip. The BIST-based approach is off-line and has been accomplished within two FPGA configurations. Each configurable logic block (CLB) can be tested independently and there is no handshaking among various CLBs' BIST cores. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results shown 100% coverage for single stuck at faults along with 19% area overhead due to additional BIST hardware and 25% increase in leakage power.

Download Full-text

Defect-oriented mixed-level fault simulation in digital systems

Facta universitatis - series Electronics and Energetics ◽

10.2298/fuee0201123u ◽

2002 ◽

Vol 15 (1) ◽

pp. 123-136

Author(s):

Raimund Ubar ◽

Jaan Raik ◽

Eero Ivask ◽

Marina Brik

Keyword(s):

Fault Simulation ◽

Register Transfer Level ◽

Digital Systems ◽

Decision Diagrams ◽

Simulation Methods ◽

Test Quality ◽

Quality Estimation ◽

Uniform Model ◽

Physical Defects ◽

Logic Level

A new method for mixed level defect-oriented fault simulation of Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gate- and RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods.

Download Full-text

Creating a standard method of controlling digital microscopes: the microscope access protocol (map)

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100136453 ◽

1995 ◽

Vol 53 ◽

pp. 16-17

Author(s):

T. A. Dodson ◽

E. Völkl ◽

L. F. Allard ◽

T. A. Nolan

Keyword(s):

Data Storage ◽

Storage Systems ◽

Digital Systems ◽

Data Networks ◽

Digital Microscopy ◽

Command Language ◽

Access Protocol ◽

Analog To Digital ◽

Basic Physics ◽

Scanning Electron

The process of moving to a fully digital microscopy laboratory requires changes in instrumentation, computing hardware, computing software, data storage systems, and data networks, as well as in the operating procedures of each facility. Moving from analog to digital systems in the microscopy laboratory is similar to the instrumentation projects being undertaken in many scientific labs. A central problem of any of these projects is to create the best combination of hardware and software to effectively control the parameters of data collection and then to actually acquire data from the instrument. This problem is particularly acute for the microscopist who wishes to "digitize" the operation of a transmission or scanning electron microscope. Although the basic physics of each type of instrument and the type of data (images & spectra) generated by each are very similar, each manufacturer approaches automation differently. The communications interfaces vary as well as the command language used to control the instrument.

Download Full-text