scholarly journals RISC-V Based Safety System-on-Chip with Hardware Comparator

2021 ◽  
Author(s):  
Eike Hahn ◽  
Dominik Kalinowski ◽  
Waldemar Mueller ◽  
Mohamed Abdelawwad ◽  
Josef Boercsoek
Keyword(s):  
Fault Tolerance ◽  
Open Source ◽  
System On Chip ◽  
Safety System ◽  
Instruction Set ◽  
On Chip ◽  
Xilinx Fpga ◽  
Ethernet Interface

In this paper, a Safety System-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed. The SSoC is implemented on a Xilinx FPGA system and extended with standard peripherals from the Xilinx IP library and from Cobham Gaisler, so that the overall system has an Ethernet interface in addition to GPIO and UART. The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input to output based on the freely available RISC-V instruction set and prove its feasibility.

scholarly journals SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication

2008 ◽  
Vol 2008 ◽  
pp. 1-10
Author(s):  
Sami Boukhechem ◽  
El-Bay Bourennane
Keyword(s):  
Open Source ◽  
System On Chip ◽  
Open Architecture ◽  
Multiprocessor System ◽  
Instruction Set ◽  
Levels Of Abstraction ◽  
Transaction Level Modeling ◽  
Synthesis Tool ◽  
Transaction Level ◽  
On Chip

Transaction-level modeling (TLM) is a promising technique to deal with the increasing complexity of modern embedded systems. This model allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. For this purpose, we use systemC, which is proposed as a standardized modeling language. This paper presents a transaction-level modeling cosimulation methodology for modeling, validating, and verifying our embedded open architecture platform. The proposed platform is an open source multiprocessor system-on-chip (MPSoC) platform, integrated under the synthesis tool for adaptive and reconfigurable system-on-chip (STARSoC) environment. It relies on the integration between an open source instruction set simulators (ISSs), OR1Ksim platform, and the systemC simulation environment which contains other components (wishbone bus, memories, , etc.). The aim of this work is to provide designers with the possibility of faster and efficient architecture exploration at a higher level of abstractions, starting from an algorithmic description to implementation details.

VLSI AND SYSTEM-ON-CHIP REDUNDANT COMPONENTS SYNTHESIS

2018 ◽  
pp. 33-39
Author(s):  
V. V. Rozanov ◽  
E. A. Suvorova
Keyword(s):  
Fault Tolerance ◽  
Integrated Circuit ◽  
System On Chip ◽  
Point Of View ◽  
Manufacturing Defects ◽  
Asic Design ◽  
Hardware Description ◽  
Early Design Stages ◽  
Chip Testing ◽  
On Chip

Redundancy - mostly used method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault tolerance. From Application Specified Integrated Circuit (ASIC) design point of view redundancy means area and power increasing. On early design stages, it is necessary to see the correlation between the components hardware description and its synthesized equivalent. The article considers several variants of synthesized redundant components that show the effect on area and power regarding to their architecture. The main goal of presented research is to describe RTL and Synthesis correlation.

Optimizing Fault Tolerance for Multi-Processor System-on-Chip

2011 ◽  
pp. 66-91 ◽  
Author(s):  
Dimitar Nikolov ◽  
Mikael Väyrynen ◽  
Urban Ingelsson ◽  
Virendra Singh ◽  
Erik Larsson
Keyword(s):  
Fault Tolerance ◽  
Error Probability ◽  
Fault Tolerant ◽  
General Purpose ◽  
System On Chip ◽  
Probability Estimation ◽  
Communication Overhead ◽  
Mathematical Framework ◽  
Safety Critical ◽  
On Chip

While the rapid development in semiconductor technologies makes it possible to manufacture integrated circuits (ICs) with multiple processors, so called Multi-Processor System-on-Chip (MPSoC), ICs manufactured in recent semiconductor technologies are becoming increasingly susceptible to transient faults, which enforces fault tolerance. Work on fault tolerance has mainly focused on safety-critical applications; however, the development of semiconductor technologies makes fault tolerance also needed for general-purpose systems. Different from safety-critical systems where meeting hard deadlines is the main requirement, it is for general-purpose systems more important to minimize the average execution time (AET). The contribution of this chapter is two-fold. First, the authors present a mathematical framework for the analysis of AET. Their analysis of AET is performed for voting, rollback recovery with checkpointing (RRC), and the combination of RRC and voting (CRV) where for a given job and soft (transient) error probability, the authors define mathematical formulas for each of the fault-tolerant techniques with the objective to minimize AET while taking bus communication overhead into account. And, for a given number of processors and jobs, the authors define integer linear programming models that minimize AET including communication overhead. Second, as error probability is not known at design time and it can change during operation, they present two techniques, periodic probability estimation (PPE) and aperiodic probability estimation (APE), to estimate the error probability and adjust the fault tolerant scheme while the IC is in operation.

scholarly journals A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

2011 ◽  
Vol 2011 ◽  
pp. 1-15 ◽  
Author(s):  
Onur Derin ◽  
Erkan Diken ◽  
Leandro Fiorin
Keyword(s):  
Fault Tolerance ◽  
Open Source ◽  
Execution Time ◽  
Initial Step ◽  
Network On Chip ◽  
Distributed Model ◽  
Total Execution Time ◽  
Process Networks ◽  
Kahn Process ◽  
On Chip

Kahn process networks (KPNs) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network on Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-Adaptive Component Run Time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.

scholarly journals IOb-Cache: A High-Performance Configurable Open-Source Cache

Algorithms ◽  
2021 ◽  
Vol 14 (8) ◽  
pp. 218
Author(s):  
João V. Roque ◽  
João D. Lopes ◽  
Mário P. Véstias ◽  
José T. de Sousa
Keyword(s):  
Open Source ◽  
High Performance ◽  
System On Chip ◽  
Processing Unit ◽  
Central Processing ◽  
Front End ◽  
Front End Module ◽  
Memory Accesses ◽  
On Chip ◽  
Access Policies

Open-source processors are increasingly being adopted by the industry, which requires all sorts of open-source implementations of peripherals and other system-on-chip modules. Despite the recent advent of open-source hardware, the available open-source caches have low configurability, limited lack of support for single-cycle pipelined memory accesses, and use non-standard hardware interfaces. In this paper, the IObundle cache (IOb-Cache), a high-performance configurable open-source cache is proposed, developed and deployed. The cache has front-end and back-end modules for fast integration with processors and memory controllers. The front-end module supports the native interface, and the back-end module supports the native interface and the standard Advanced eXtensible Interface (AXI). The cache is highly configurable in structure and access policies. The back-end can be configured to read bursts of multiple words per transfer to take advantage of the available memory bandwidth. To the best of our knowledge, IOb-Cache is currently the only configurable cache that supports pipelined Central Processing Unit (CPU) interfaces and AXI memory bus interface. Additionally, it has a write-through buffer and an independent controller for fast, most of the time 1-cycle writing together with 1-cycle reading, while previous works only support 1-cycle reading. This allows the best clocks-per-Instruction (CPI) to be close to one (1.055). IOb-Cache is integrated into IOb System-on-Chip (IOb-SoC) Github repository, which has 29 stars and is already being used in 50 projects (forks).

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