VLSI AND SYSTEM-ON-CHIP REDUNDANT COMPONENTS SYNTHESIS

2018 ◽  
pp. 33-39
Author(s):  
V. V. Rozanov ◽  
E. A. Suvorova
Keyword(s):  
Fault Tolerance ◽  
Integrated Circuit ◽  
System On Chip ◽  
Point Of View ◽  
Manufacturing Defects ◽  
Asic Design ◽  
Hardware Description ◽  
Early Design Stages ◽  
Chip Testing ◽  
On Chip

Redundancy - mostly used method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault tolerance. From Application Specified Integrated Circuit (ASIC) design point of view redundancy means area and power increasing. On early design stages, it is necessary to see the correlation between the components hardware description and its synthesized equivalent. The article considers several variants of synthesized redundant components that show the effect on area and power regarding to their architecture. The main goal of presented research is to describe RTL and Synthesis correlation.

scholarly journals Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Maher Assaad ◽  
Mohammed H. Alser
Keyword(s):  
Integrated Circuit ◽  
Reference Signal ◽  
Digital Processing ◽  
System On Chip ◽  
Frequency Multiplier ◽  
Experimental Results ◽  
Clock Signal ◽  
Phase Tracking ◽  
Frequency Locked Loops ◽  
On Chip

This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all-digital dual-loop delay- and frequency-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit. Moreover, it can be used in supplying a clock reference for distributed digital processing systems as well as intra/interchip communication in system-on-chip (SoC). The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. The experimental results validate the expected phase tracking as well as the synthesizing properties. For the measurement and validation purpose, an input reference signal in the range of 1.94–2.62 MHz was injected; the generated clock signal has a higher frequency, and it is in the range of 124.2–167.9 MHz with a frequency step (i.e., resolution) of 0.168 MHz. The synthesized design requires 330 logic elements using the above Altera board.

Hybrid BIST energy minimisation technique for system-on-chip testing

2006 ◽  
Vol 153 (4) ◽  
pp. 208 ◽  
Author(s):  
G. Jervan ◽  
Z. Peng ◽  
T. Shchenova ◽  
R. Ubar
Keyword(s):  
System On Chip ◽  
Energy Minimisation ◽  
Chip Testing ◽  
On Chip

scholarly journals Design of AMBA AXI4 protocol for System-on-Chip communication

2012 ◽  
pp. 38-42
Author(s):  
Shaila S Math ◽  
Manjula R B
Keyword(s):  
System On Chip ◽  
Hardware Description Language ◽  
Test Cases ◽  
Description Language ◽  
Write Response ◽  
Hardware Description ◽  
Simulation Results ◽  
On Chip ◽  
Ip Blocks ◽  
Bus Architecture

Advanced microcontroller bus architecture (AMBA) protocol family provides metric-driven verification of protocol compliance, enabling comprehensive testing of interface intellectual property (IP) blocks and system-on-chip (SoC) designs. The AMBA advanced extensible interface 4 (AXI4) update to AMBA AXI3 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI4 also includes information on the interoperability of components. AMBA AXI4 protocol system supports 16 masters and 16 slaves interfacing. This paper presents a work aimed to design the AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are shown in Verilog compiler simulator (VCS) tool. The operating frequency is set to 100MHz. Two test cases are run to perform multiple read and multiple write operations. To perform single read operation module takes 160ns and for single write operation it takes 565ns.

scholarly journals A System-on-Chip Solution for a Low Power Active Capsule Endoscope with Therapeutic Capabilities for Clip Application in the Gastrointestinal Tract

2017 ◽  
Vol 02 (04) ◽  
pp. 1750005
Author(s):  
Oscar Alonso ◽  
Angel Diéguez ◽  
Sebastian Schostek ◽  
Marc O. Schurr
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
System On Chip ◽  
Capsule Endoscope ◽  
Implementation Challenges ◽  
Clip Application ◽  
Application Specific Integrated Circuit ◽  
On Chip ◽  
Wireless Capsule ◽  
Application Specific

This paper addresses the circuit implementation challenges resulting from the integration of a therapeutic clip in a magnetically maneuverable wireless capsule intended for colonoscopy. To deal with the size constraints typical of a capsule endoscope, an Application Specific Integrated Circuit (ASIC) has been designed specifically to habilitate the release of the therapeutic clip. The ASIC is a complete System on Chip (SoC) that incorporates a circuit for the low power release of the clip, thus overcoming the limitations of the power supply system. With a size of 14[Formula: see text]mm2, the ASIC can be incorporated in practically any capsule endoscope, consuming only an idle-state power of 1.5[Formula: see text]mW.

Optimizing Fault Tolerance for Multi-Processor System-on-Chip

2011 ◽  
pp. 66-91 ◽  
Author(s):  
Dimitar Nikolov ◽  
Mikael Väyrynen ◽  
Urban Ingelsson ◽  
Virendra Singh ◽  
Erik Larsson
Keyword(s):  
Fault Tolerance ◽  
Error Probability ◽  
Fault Tolerant ◽  
General Purpose ◽  
System On Chip ◽  
Probability Estimation ◽  
Communication Overhead ◽  
Mathematical Framework ◽  
Safety Critical ◽  
On Chip

While the rapid development in semiconductor technologies makes it possible to manufacture integrated circuits (ICs) with multiple processors, so called Multi-Processor System-on-Chip (MPSoC), ICs manufactured in recent semiconductor technologies are becoming increasingly susceptible to transient faults, which enforces fault tolerance. Work on fault tolerance has mainly focused on safety-critical applications; however, the development of semiconductor technologies makes fault tolerance also needed for general-purpose systems. Different from safety-critical systems where meeting hard deadlines is the main requirement, it is for general-purpose systems more important to minimize the average execution time (AET). The contribution of this chapter is two-fold. First, the authors present a mathematical framework for the analysis of AET. Their analysis of AET is performed for voting, rollback recovery with checkpointing (RRC), and the combination of RRC and voting (CRV) where for a given job and soft (transient) error probability, the authors define mathematical formulas for each of the fault-tolerant techniques with the objective to minimize AET while taking bus communication overhead into account. And, for a given number of processors and jobs, the authors define integer linear programming models that minimize AET including communication overhead. Second, as error probability is not known at design time and it can change during operation, they present two techniques, periodic probability estimation (PPE) and aperiodic probability estimation (APE), to estimate the error probability and adjust the fault tolerant scheme while the IC is in operation.

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