A Review of Parallel Heterogeneous Computing Algorithms in Power Systems

The power system expansion and the integration of technologies, such as renewable generation, distributed generation, high voltage direct current, and energy storage, have made power system simulation challenging in multiple applications. The current computing platforms employed for planning, operation, studies, visualization, and the analysis of power systems are reaching their operational limit since the complexity and size of modern power systems results in long simulation times and high computational demand. Time reductions in simulation and analysis lead to the better and further optimized performance of power systems. Heterogeneous computing—where different processing units interact—has shown that power system applications can take advantage of the unique strengths of each type of processing unit, such as central processing units, graphics processing units, and field-programmable gate arrays interacting in on-premise or cloud environments. Parallel Heterogeneous Computing appears as an alternative to reduce simulation times by optimizing multitask execution in parallel computing architectures with different processing units working together. This paper presents a review of Parallel Heterogeneous Computing techniques, how these techniques have been applied in a wide variety of power system applications, how they help reduce the computational time of modern power system simulation and analysis, and the current tendency regarding each application. We present a wide variety of approaches classified by technique and application.

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Controllers: An abstraction to ease the use of hardware accelerators

The International Journal of High Performance Computing Applications ◽

10.1177/1094342017702962 ◽

2017 ◽

Vol 32 (6) ◽

pp. 838-853 ◽

Cited By ~ 4

Author(s):

Ana Moreton–Fernandez ◽

Hector Ortega–Arranz ◽

Arturo Gonzalez–Escribano

Keyword(s):

Graphics Processing Units ◽

High Performance ◽

Abstract Entity ◽

Hardware Accelerators ◽

Processing Unit ◽

Central Processing ◽

Computing Platforms ◽

Graphics Processing ◽

Performance Computing ◽

Selection Of

Nowadays the use of hardware accelerators, such as the graphics processing units or XeonPhi coprocessors, is key in solving computationally costly problems that require high performance computing. However, programming solutions for an efficient deployment for these kind of devices is a very complex task that relies on the manual management of memory transfers and configuration parameters. The programmer has to carry out a deep study of the particular data that needs to be computed at each moment, across different computing platforms, also considering architectural details. We introduce the controller concept as an abstract entity that allows the programmer to easily manage the communications and kernel launching details on hardware accelerators in a transparent way. This model also provides the possibility of defining and launching central processing unit kernels in multi-core processors with the same abstraction and methodology used for the accelerators. It internally combines different native programming models and technologies to exploit the potential of each kind of device. Additionally, the model also allows the programmer to simplify the proper selection of values for several configuration parameters that can be selected when a kernel is launched. This is done through a qualitative characterization process of the kernel code to be executed. Finally, we present the implementation of the controller model in a prototype library, together with its application in several case studies. Its use has led to reductions in the development and porting costs, with significantly low overheads in the execution times when compared to manually programmed and optimized solutions which directly use CUDA and OpenMP.

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State Estimation Based on Ensemble DA–DSVM in Power System

International Journal of Software Engineering and Knowledge Engineering ◽

10.1142/s0218194019400023 ◽

2019 ◽

Vol 29 (05) ◽

pp. 653-669

Author(s):

Shunjiang Wang ◽

Baoming Pu ◽

Ming Li ◽

Weichun Ge ◽

Qianwei Liu ◽

...

Keyword(s):

Power Systems ◽

Power System ◽

State Estimation ◽

Graphics Processing Unit ◽

Estimation Algorithm ◽

The State ◽

Support Vector ◽

Processing Unit ◽

Central Processing ◽

Calculation Results

This paper investigates the state estimation problem of power systems. A novel, fast and accurate state estimation algorithm is presented to solve this problem based on the one-dimensional denoising autoencoder and deep support vector machine (1D DA–DSVM). Besides, for further reducing the computation burden, a partitioning method is presented to divide the power system into several sub-networks and the proposed algorithm can be applied to each sub-network. A hybrid computing architecture of Central Processing Unit (CPU) and Graphics Processing Unit (GPU) is employed in the overall state estimation, in which the GPU is used to estimate each sub-network and the CPU is used to integrate all the calculation results and output the state estimate. Simulation results show that the proposed method can effectively improve the accuracy and computational efficiency of the state estimation of power systems.

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A New FPGA-Based Real-Time Digital Solver for Power System Simulation

Energies ◽

10.3390/en12244666 ◽

2019 ◽

Vol 12 (24) ◽

pp. 4666 ◽

Cited By ~ 3

Author(s):

Bingda Zhang ◽

Xianglong Jin ◽

Sijia Tu ◽

Zhao Jin ◽

Jie Zhang

Keyword(s):

Power Systems ◽

Power System ◽

Real Time ◽

System Simulation ◽

Digital Simulation ◽

Data Communication ◽

Power System Simulation ◽

Simulation Based ◽

Field Programmable ◽

The Look

Considering the rational use of field programmable gate array (FPGA) resources, this paper proposes a new FPGA-based real-time digital solver (FRTDS) for power system simulation. Based on the relationship between the number of computing components, the operating frequency, and the pipeline length, the best selection principle is given. By analyzing the implementation method of the Multi-Port Read/Write Circuit, the computing formula of the Look-Up-Table (LUT) consumption was derived. Given the excessive use of LUTs in the original computing components, the computing components were assembled in a single typical arithmetic expression of the power system simulation program, as the basic computing formula was characterized by a subset of the typical computing formula and multiple uses of the same variable. Data communication between different computing components was realized by using Multi-Port Input Circuits that share some outputs of read controller, and Multi-Port Output Circuits, which share some outputs of computing cores. According to the test results of original FRTDS and new FRTDS, it was found that the solution proposed in this paper had a shorter ideal simulation time and a higher parallel computing capability, which was very suitable for real-time digital simulation of power systems.

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Power System Simulation Laboratory as a Modern Educational Tool

International Journal of Systems Applications, Engineering & Development ◽

10.46300/91015.2021.15.27 ◽

2021 ◽

Vol 15 ◽

pp. 186-193

Author(s):

Antans Sauhats ◽

Diana Zalostiba ◽

Aleksandrs Dolgicers ◽

Andrejs Utans ◽

Galina Bochkarjova ◽

...

Keyword(s):

Power Systems ◽

Power System ◽

Research Laboratory ◽

System Simulation ◽

Simulation Software ◽

Practical Skills ◽

Educational Tool ◽

Power System Simulation ◽

Protective Relaying ◽

Digital Input

To ensure the success of the personnel of power systems are required not only deep theoretical knowledge’s but also practical skills, the acquisition of which in modern universities is associated with considerable difficulties. The paper provides an overview of opportunities to overcome part of these difficulties by creating automation and protective relaying testing educational and research laboratory. To generate testing signals power system emergency processes records and simulation software are used. For education purposes microprocessorbased, suitable for digital input testing signals terminal is created

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