scholarly journals Laser-Induced Period Surface Structures to Improve Solderability of Electrical Solder Pads

2021 ◽  
Vol 12 (1) ◽  
pp. 80
Author(s):  
Stefan Rung ◽  
Ralf Hellmann
Keyword(s):  
Femtosecond Laser ◽  
Printed Circuit Boards ◽  
Modulation Depth ◽  
Surface Structures ◽  
Spatial Period ◽  
Solder Paste ◽  
Circuit Boards ◽  
Periodic Surface ◽  
Frequency Laser ◽  
Free Solder

We report on structuring copper representing soldering pads of printed circuit boards by laser-induced periodic surface structures. Femtosecond laser radiation is used to generate low spatial frequency laser-induced surface structures, having a spatial period of 992 nm and a modulation depth of 120 nm, respectively. The slump of screen-printed solder paste is measured to compare the solder coverage on the pads after the solder process on a hot plate. A comparative study of the coverage of solder paste on a fresh polished pad, a pad stored for two weeks, and femtosecond laser-structured pads reveals the improved wettability of structured pads even after storage. In addition, leaded and lead-free solder pads are compared with the particular advantages of the solder-free pad when periodically laser structured. Our findings are attributed to two major effects: namely, the increase of the surface area and the improved surface chemical wettability. Overall, the application of laser-induced periodic surface structures helps to reduce the demand of lead-based solder in the electronic industry and provides a feasible method for a fast and spatial selective way of surface functionalization.

scholarly journals Evaluation of The Printability of Lead Versus Lead Free Solder Pastes

2021 ◽  
Author(s):  
Ala Al Robiaee
Keyword(s):  
Printed Circuit Boards ◽  
Lead Free ◽  
Solder Paste ◽  
Circuit Boards ◽  
Stencil Printing ◽  
Printed Circuit ◽  
Main Factors ◽  
Free Solder ◽  
Print Process ◽  
The Impact

As the global marketplaces consider mandating lead-free equipments, many questions arise about the impact and feasibility of replacing lead in printed circuit boards soldering applications. In this project, the results presented of a study on comparing the process of screening lead paste versus lead free paste parameters for regular stencil printing using standard manufacturing methods. The key process parameters studies were: squeegee speed, squeegee pressure, and screening yield for both types of pastes. Two solder paste formulations (lead paste and lead-free paste) were evaluated in this study. The analysis of the pastes deposit volumes showed that for normal manufacturing range of printer (screener) settings (speed and pressure) tested the two pastes performed the same. The results also showed that the squeegee speed has a greater effect on the printing process than the squeegee pressure. The tests clearly showed that the lead paste was affected more by setting changes compared to the lead free paste. Varying the print speed and pressure for type of pastes by observing the resulting printed paste volumes optimized screening parameters. This study confirms that a new stencil or stencil design is not needed for the lead free paste. However, this study recommends a change to the sitting of the screening print process. Stencil cleaning frequency is one of the main factors that impact the production rate in an SMT line. The project highlights new results that lead free paste throughput will be less compared to lead paste at the screening step. The number of rejected boards screened with lead free-paste exceeded normal manufacturing standards. As stencil cleaning is a must function, it was recommended to increase stencil wiping frequency when lead free paste [is] in use in order to obtain a consistent volume with less screening defect.

Reliability of an 1657CCGA (Ceramic Column Grid Array) Package With 95.5Sn3.9Ag0.6Cu Lead-Free Solder Paste on PCBs (Printed Circuit Boards)

2003 ◽  
Author(s):  
John Lau ◽  
Walter Dauksher
Keyword(s):  
Fatigue Life ◽  
Thermal Fatigue ◽  
Printed Circuit Boards ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Thermal Fatigue Life ◽  
Free Solder

In many applications such as computers and telecommunications, the IC chip sizes are very big, the on-chip frequency and power dissipation are very high, and the number of chip I/Os is very large. The CCGA (ceramic column grid array) package developed by IBM is one of the best candidates for housing these kinds of chips [1–7]. There are two parts in this study. One is to show that the 2-parameter Weibull life distribution is adequate for modeling the thermal-fatigue life of lead-free solder joints. This is demonstrated by comparing the 2-parameter and 3-parameter Weibull distributions with life test data of an 1657-pin CCGA package with the 95.5wt%Sn3.9wt%Ag0.6wt%Cu lead-free solder paste on lead-free PCBs (printed circuit boards) under thermal cycling conditions. The other part of this study is to determine the time-history creep strain energy density of the 1657-pin CCGA solder column with two different solder paste materials, namely, 95.5wt%Sn3.9wt%Ag0.6wt%Cu and 63wt%Sn37wt%Pb and under three different thermal cycling profiles, namely, 25 ↔ 75°C, 0 ↔ 100°C, and −25 ↔ 125°C. The effects of these solder pastes and temperature conditions on the thermal-fatigue life of the high-lead (10wt%Sn90wt%Pb) solder columns of the CCGA package are provided and discussed.

scholarly journals Multi-Angular Colorimetric Responses of Uni- and Omni-Directional Femtosecond Laser-Induced Periodic Surface Structures on Metals

Nanomaterials ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 2010
Author(s):  
Taek-Yong Hwang ◽  
Yong-dae Kim ◽  
Jongweon Cho ◽  
Hai-Joong Lee ◽  
Hyo-Soo Lee ◽  
...  
Keyword(s):  
Laser Pulse ◽  
Femtosecond Laser ◽  
Spatial Frequency ◽  
Femtosecond Laser Pulse ◽  
Metal Surfaces ◽  
Surface Structures ◽  
Pulse Irradiation ◽  
Periodic Surface ◽  
Frequency Laser ◽  
Angle Of Reflection

We investigated the colorimetric behaviors of metal surfaces with unidirectional low-spatial-frequency laser-induced periodic surface structures (UD-LSFLs) and omnidirectional LSFLs (OD-LSFLs) fabricated using femtosecond laser pulse irradiation. With the CIE standard illuminant D65, incident at −45°, we show that UD-LSFLs on metals transform polished metals to gonio-apparent materials with a unique behavior of colorimetric responses, depending on both the detection and rotation angles, whereas OD-LSFLs have nearly uniform gonio-apparent colors at each detection angle, regardless of their rotation. These colorimetric behaviors can be observed not only at the angles of diffraction but also near the angle of reflection, and we find that the power redistribution due to Rayleigh anomalies also plays an important role in the colorimetric responses of UD- and OD-LSFLs, in addition to diffraction.

Reliability of an 1657CCGA (Ceramic Column Grid Array) Package With 95.5SN3.9AG0.6CU Lead-Free Solder Paste on PCBS (Printed Circuit Boards)

2005 ◽  
Vol 127 (2) ◽  
pp. 96-105 ◽  
Author(s):  
John Lau ◽  
Walter Dauksher
Keyword(s):  
Fatigue Life ◽  
Printed Circuit Boards ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Thermal Fatigue Life ◽  
Free Solder ◽  
Two Parameter

In many applications such as computers and telecommunications, the IC chip sizes are very big, the on-chip frequency and power dissipation are very high, and the number of chip I/Os is very large. The CCGA (ceramic column grid array) package developed by IBM is one of the best candidates for housing these kinds of chips. There are two parts in this study. One is to show that the two-parameter Weibull life distribution is adequate for modeling the thermal-fatigue life of lead-free solder joints. This is demonstrated by comparing the two-parameter and three-parameter Weibull distributions with life test data of an 1657-pin CCGA package with the 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu lead-free solder paste on lead-free printed circuit boards under thermal cycling conditions. The other part of this study is to determine the time-history creep strain energy density of the 1657-pin CCGA solder column with two different solder paste materials, namely, 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu and 63 wt %Sn37 wt %Pb and under three different thermal cycling profiles, namely, 25↔75°C, 0↔100°C, and −25↔125°C. The effects of these solder pastes and temperature conditions on the thermal-fatigue life of the high-lead (10 wt %Sn90 wt %Pb) solder columns of the CCGA package are provided and discussed.

scholarly journals Evaluation of The Printability of Lead Versus Lead Free Solder Pastes

2021 ◽  
Author(s):  
Ala Al Robiaee
Keyword(s):  
Printed Circuit Boards ◽  
Lead Free ◽  
Solder Paste ◽  
Circuit Boards ◽  
Stencil Printing ◽  
Printed Circuit ◽  
Main Factors ◽  
Free Solder ◽  
Print Process ◽  
The Impact

As the global marketplaces consider mandating lead-free equipments, many questions arise about the impact and feasibility of replacing lead in printed circuit boards soldering applications. In this project, the results presented of a study on comparing the process of screening lead paste versus lead free paste parameters for regular stencil printing using standard manufacturing methods. The key process parameters studies were: squeegee speed, squeegee pressure, and screening yield for both types of pastes. Two solder paste formulations (lead paste and lead-free paste) were evaluated in this study. The analysis of the pastes deposit volumes showed that for normal manufacturing range of printer (screener) settings (speed and pressure) tested the two pastes performed the same. The results also showed that the squeegee speed has a greater effect on the printing process than the squeegee pressure. The tests clearly showed that the lead paste was affected more by setting changes compared to the lead free paste. Varying the print speed and pressure for type of pastes by observing the resulting printed paste volumes optimized screening parameters. This study confirms that a new stencil or stencil design is not needed for the lead free paste. However, this study recommends a change to the sitting of the screening print process. Stencil cleaning frequency is one of the main factors that impact the production rate in an SMT line. The project highlights new results that lead free paste throughput will be less compared to lead paste at the screening step. The number of rejected boards screened with lead free-paste exceeded normal manufacturing standards. As stencil cleaning is a must function, it was recommended to increase stencil wiping frequency when lead free paste [is] in use in order to obtain a consistent volume with less screening defect.

Conductive Filament Formation in Printed Circuit Boards – Effects of Reflow Conditions and Flame Retardants

2009 ◽  
Author(s):  
Bhanu Sood ◽  
Michael Pecht
Keyword(s):  
Flame Retardants ◽  
Printed Circuit Boards ◽  
Electrochemical Process ◽  
Lead Free ◽  
Circuit Boards ◽  
Filament Formation ◽  
Conductive Filament ◽  
Printed Circuit ◽  
Free Solder ◽  
Halogen Free

Abstract Failures in printed circuit boards account for a significant percentage of field returns in electronic products and systems. Conductive filament formation is an electrochemical process that requires the transport of a metal through or across a nonmetallic medium under the influence of an applied electric field. With the advent of lead-free initiatives, boards are being exposed to higher temperatures during lead-free solder processing. This can weaken the glass-fiber bonding, thus enhancing conductive filament formation. The effect of the inclusion of halogen-free flame retardants on conductive filament formation in printed circuit boards is also not completely understood. Previous studies, along with analysis and examinations conducted on printed circuit boards with failure sites that were due to conductive filament formation, have shown that the conductive path is typically formed along the delaminated fiber glass and epoxy resin interfaces. This paper is a result of a year-long study on the effects of reflow temperatures, halogen-free flame retardants, glass reinforcement weave style, and conductor spacing on times to failure due to conductive filament formation.

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