Reliability testing and data analysis of an 1657CCGA (ceramic column grid array) package with lead-free solder paste on lead-free PCBs (printed circuit boards)

2004 ◽  
Author(s):  
J. Lau ◽  
W. Dauksher ◽  
E. Ott ◽  
D. Shangguan ◽  
J. Smetana ◽  
...  
Keyword(s):  
Data Analysis ◽  
Printed Circuit Boards ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Reliability Testing ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Free Solder

Reliability of an 1657CCGA (Ceramic Column Grid Array) Package With 95.5Sn3.9Ag0.6Cu Lead-Free Solder Paste on PCBs (Printed Circuit Boards)

2003 ◽  
Author(s):  
John Lau ◽  
Walter Dauksher
Keyword(s):  
Fatigue Life ◽  
Thermal Fatigue ◽  
Printed Circuit Boards ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Thermal Fatigue Life ◽  
Free Solder

In many applications such as computers and telecommunications, the IC chip sizes are very big, the on-chip frequency and power dissipation are very high, and the number of chip I/Os is very large. The CCGA (ceramic column grid array) package developed by IBM is one of the best candidates for housing these kinds of chips [1–7]. There are two parts in this study. One is to show that the 2-parameter Weibull life distribution is adequate for modeling the thermal-fatigue life of lead-free solder joints. This is demonstrated by comparing the 2-parameter and 3-parameter Weibull distributions with life test data of an 1657-pin CCGA package with the 95.5wt%Sn3.9wt%Ag0.6wt%Cu lead-free solder paste on lead-free PCBs (printed circuit boards) under thermal cycling conditions. The other part of this study is to determine the time-history creep strain energy density of the 1657-pin CCGA solder column with two different solder paste materials, namely, 95.5wt%Sn3.9wt%Ag0.6wt%Cu and 63wt%Sn37wt%Pb and under three different thermal cycling profiles, namely, 25 ↔ 75°C, 0 ↔ 100°C, and −25 ↔ 125°C. The effects of these solder pastes and temperature conditions on the thermal-fatigue life of the high-lead (10wt%Sn90wt%Pb) solder columns of the CCGA package are provided and discussed.

Reliability of an 1657CCGA (Ceramic Column Grid Array) Package With 95.5SN3.9AG0.6CU Lead-Free Solder Paste on PCBS (Printed Circuit Boards)

2005 ◽  
Vol 127 (2) ◽  
pp. 96-105 ◽  
Author(s):  
John Lau ◽  
Walter Dauksher
Keyword(s):  
Fatigue Life ◽  
Printed Circuit Boards ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Thermal Fatigue Life ◽  
Free Solder ◽  
Two Parameter

In many applications such as computers and telecommunications, the IC chip sizes are very big, the on-chip frequency and power dissipation are very high, and the number of chip I/Os is very large. The CCGA (ceramic column grid array) package developed by IBM is one of the best candidates for housing these kinds of chips. There are two parts in this study. One is to show that the two-parameter Weibull life distribution is adequate for modeling the thermal-fatigue life of lead-free solder joints. This is demonstrated by comparing the two-parameter and three-parameter Weibull distributions with life test data of an 1657-pin CCGA package with the 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu lead-free solder paste on lead-free printed circuit boards under thermal cycling conditions. The other part of this study is to determine the time-history creep strain energy density of the 1657-pin CCGA solder column with two different solder paste materials, namely, 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu and 63 wt %Sn37 wt %Pb and under three different thermal cycling profiles, namely, 25↔75°C, 0↔100°C, and −25↔125°C. The effects of these solder pastes and temperature conditions on the thermal-fatigue life of the high-lead (10 wt %Sn90 wt %Pb) solder columns of the CCGA package are provided and discussed.

scholarly journals Evaluation of The Printability of Lead Versus Lead Free Solder Pastes

2021 ◽  
Author(s):  
Ala Al Robiaee
Keyword(s):  
Printed Circuit Boards ◽  
Lead Free ◽  
Solder Paste ◽  
Circuit Boards ◽  
Stencil Printing ◽  
Printed Circuit ◽  
Main Factors ◽  
Free Solder ◽  
Print Process ◽  
The Impact

As the global marketplaces consider mandating lead-free equipments, many questions arise about the impact and feasibility of replacing lead in printed circuit boards soldering applications. In this project, the results presented of a study on comparing the process of screening lead paste versus lead free paste parameters for regular stencil printing using standard manufacturing methods. The key process parameters studies were: squeegee speed, squeegee pressure, and screening yield for both types of pastes. Two solder paste formulations (lead paste and lead-free paste) were evaluated in this study. The analysis of the pastes deposit volumes showed that for normal manufacturing range of printer (screener) settings (speed and pressure) tested the two pastes performed the same. The results also showed that the squeegee speed has a greater effect on the printing process than the squeegee pressure. The tests clearly showed that the lead paste was affected more by setting changes compared to the lead free paste. Varying the print speed and pressure for type of pastes by observing the resulting printed paste volumes optimized screening parameters. This study confirms that a new stencil or stencil design is not needed for the lead free paste. However, this study recommends a change to the sitting of the screening print process. Stencil cleaning frequency is one of the main factors that impact the production rate in an SMT line. The project highlights new results that lead free paste throughput will be less compared to lead paste at the screening step. The number of rejected boards screened with lead free-paste exceeded normal manufacturing standards. As stencil cleaning is a must function, it was recommended to increase stencil wiping frequency when lead free paste [is] in use in order to obtain a consistent volume with less screening defect.

OPTIMIZATION OF CHEMISTRY FOR A VAPOUR PHASE PROCESS TO DEFLUX NO CLEAN LEAD FREE MATERIALS ON PCBS

2017 ◽  
Vol 2017 (1) ◽  
pp. 000477-000481
Author(s):  
Patrick J. Duchi ◽  
Jonathan Cetier ◽  
Laurent Levasseur ◽  
Jaquemine Coquio ◽  
Rodrigo Aguilar
Keyword(s):  
Printed Circuit Boards ◽  
Vapour Phase ◽  
Lead Free ◽  
Complex Geometries ◽  
Lead Free Solder ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Solder Flux ◽  
Free Solder ◽  
2D To 3D

Abstract The cleaning action to remove baked-on solder flux residues after reflow, also known as defluxing, from printed circuit boards has become more and more challenged because of the higher densities in today's electronics, miniaturization, lower stand off components, and complex geometries where the packaging has evolved from 2D to 3D. This situation becomes even more difficult in No Clean lead free assembly where higher process temperatures are applied causing charring to flux residues. In addition, traditional chemicals like CFC's, HCFC's, brominated solvents, detergents and glycols cannot longer do a good cleaning job anymore because most flux formulations have changed. An hydrocarbon solvent used as co-solvent in vapour phase application has been re-formulated under three main criterias: environmental legislations, toxicity, and defluxing performance The results from the laboratory stage have been applied to clean the fluxes of three No Clean lead free solder pastes used in mass production of printed circuit boards assemblies with high densities interconnections and exposed to harsh environmental conditions.

scholarly journals Evaluation of The Printability of Lead Versus Lead Free Solder Pastes

2021 ◽  
Author(s):  
Ala Al Robiaee
Keyword(s):  
Printed Circuit Boards ◽  
Lead Free ◽  
Solder Paste ◽  
Circuit Boards ◽  
Stencil Printing ◽  
Printed Circuit ◽  
Main Factors ◽  
Free Solder ◽  
Print Process ◽  
The Impact

As the global marketplaces consider mandating lead-free equipments, many questions arise about the impact and feasibility of replacing lead in printed circuit boards soldering applications. In this project, the results presented of a study on comparing the process of screening lead paste versus lead free paste parameters for regular stencil printing using standard manufacturing methods. The key process parameters studies were: squeegee speed, squeegee pressure, and screening yield for both types of pastes. Two solder paste formulations (lead paste and lead-free paste) were evaluated in this study. The analysis of the pastes deposit volumes showed that for normal manufacturing range of printer (screener) settings (speed and pressure) tested the two pastes performed the same. The results also showed that the squeegee speed has a greater effect on the printing process than the squeegee pressure. The tests clearly showed that the lead paste was affected more by setting changes compared to the lead free paste. Varying the print speed and pressure for type of pastes by observing the resulting printed paste volumes optimized screening parameters. This study confirms that a new stencil or stencil design is not needed for the lead free paste. However, this study recommends a change to the sitting of the screening print process. Stencil cleaning frequency is one of the main factors that impact the production rate in an SMT line. The project highlights new results that lead free paste throughput will be less compared to lead paste at the screening step. The number of rejected boards screened with lead free-paste exceeded normal manufacturing standards. As stencil cleaning is a must function, it was recommended to increase stencil wiping frequency when lead free paste [is] in use in order to obtain a consistent volume with less screening defect.

Newly Developed Real Time Monitoring System for Ionic Migration by Means of Quartz Crystal Microbalance (QCM) and Electrochemical Impedance Spectroscopy (EIS)

2003 ◽  
Author(s):  
Sachio Yoshihara
Keyword(s):  
Anodic Dissolution ◽  
Quartz Crystal ◽  
Printed Circuit Boards ◽  
Electrochemical Impedance ◽  
Lead Free ◽  
Lead Free Solder ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Dissolution Reaction ◽  
Free Solder

Micro-fabricated or Nano-fabricated Printed Circuit Boards (PCB) using environmental friendly materials and processes will be desirable candidates for future electronic packaging technologies. To investigate the ionic migration for thus developed PCB, quite new measurement method has been developed by the authors, which enables real time monitoring of the growth process of ionic migration using QCM (Quartz Crystal Microbalance) and Electrochemical Impedance Spectroscopy (EIS). First part of this research has focused on the QCM method and EIS to study the process of ion migration (hereinafter we call it simply “migration”) in various types of lead-free solder plating and the effects of the reflow (Heat treatments) processing and flux residue of soldering processes. In addition, we investigated the anodic dissolution characteristics of the elements in each type of solder alloy by measuring the current-potential curves in 0.1 kmol m−3 KNO3 solution. When using Sn-3.5 mass%Ag solder plating, reflow processing segregate the stable compound Ag3Sn layer and Sn layer. The Sn layer selectively promotes the anodic dissolution reaction, increasing the occurrence of migration. When using Sn-9 mass%Zn solder plating, the Sn effectively prevents the excessive dissolution reaction of Zn. However, since reflow processing causes each element to separate out, reflow processing lessens the effectiveness of Sn, thus promoting the occurrence of migration. The flux processing of lead-free solders suppresses anodic dissolution and effectively prevents the occurrence of migration. However, with Sn-9 mass%Zn, the lowered adhesion between the flux film and the electrodes is a factor in speeding the growth of migration. The ionic migration of lead free solder in severe NOx circumstance will be commented. Next, electric reliability of the newly developed copper printed boards by NEDO project (L/S = 4/6, 8/12, 12/16 μ□) using polyimide as the substrate have been evaluated under 85 °C, 85%RH. The generation of the migration was tested by conventional time dependence of current under bias of 5.0 V. The progress of the migration could be investigated by EIS (Cole-Cole plots of the impedance). The degradation of the diameter of the impedance loop suggested the intimation of migrations. Finally, in order to establish the micro-fabricated printed circuit boards, “semi-additive” process will be one of the candidates. The process involves the copper etching processes by use of FeCl3 or CuCl2 aqueous solution. But even after the cleansing of such etched substrate, some residue of the iron or copper contaminants will affect the electric reliability of the boards. Such effects have been evaluated by the QCM method. The obtained results suggested that scarce residue of iron contaminants will diminish the reliability rather than residue of copper contaminants.

Conductive Filament Formation in Printed Circuit Boards – Effects of Reflow Conditions and Flame Retardants

2009 ◽  
Author(s):  
Bhanu Sood ◽  
Michael Pecht
Keyword(s):  
Flame Retardants ◽  
Printed Circuit Boards ◽  
Electrochemical Process ◽  
Lead Free ◽  
Circuit Boards ◽  
Filament Formation ◽  
Conductive Filament ◽  
Printed Circuit ◽  
Free Solder ◽  
Halogen Free

Abstract Failures in printed circuit boards account for a significant percentage of field returns in electronic products and systems. Conductive filament formation is an electrochemical process that requires the transport of a metal through or across a nonmetallic medium under the influence of an applied electric field. With the advent of lead-free initiatives, boards are being exposed to higher temperatures during lead-free solder processing. This can weaken the glass-fiber bonding, thus enhancing conductive filament formation. The effect of the inclusion of halogen-free flame retardants on conductive filament formation in printed circuit boards is also not completely understood. Previous studies, along with analysis and examinations conducted on printed circuit boards with failure sites that were due to conductive filament formation, have shown that the conductive path is typically formed along the delaminated fiber glass and epoxy resin interfaces. This paper is a result of a year-long study on the effects of reflow temperatures, halogen-free flame retardants, glass reinforcement weave style, and conductor spacing on times to failure due to conductive filament formation.

Site Redressing Techniques and Rework of Lead-Free Chip Scale Packages

2003 ◽  
Author(s):  
Arun Gowda ◽  
Anthony Primavera ◽  
K. Srihari
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Printed Circuit ◽  
Free Solder ◽  
The Individual ◽  
Component Assembly ◽  
Free Area

The implementation of lead-free solder into an electronics assembly process necessitates the reassessment of the individual factors involved in component attachment and rework. A component assembly undergoes multiple thermal cycles during rework. With the use of lead-free solder, the assemblies are subjected to higher assembly and rework temperatures than those required for eutectic tin-lead assemblies. The rework of lead-free area array components involves the removal of defective component, preparation of the printed circuit board attachment pad (site redressing), solder paste replenishment or flux deposition, and component placement and reflow. This paper primarily focuses on the site redressing aspect of lead-free rework, followed by the development of rework processes for lead-free chip scale packages utilizing the knowledge gained in the site redressing studies.

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