scholarly journals Identifying the Optimal Subsets of Test Items through Adaptive Test for Cost Reduction of ICs

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 680
Author(s):  
Huaguo Liang ◽  
Jinlei Wan ◽  
Tai Song ◽  
Wangchao Hou

With the growing complexity of integrated circuits (ICs), more and more test items are required in testing. However, the large number of invalid items (which narrowly pass the test) continues to increase the test time and, consequently, test costs. Aiming to address the problems of long test time and reduced test item efficiency, this paper presents a method which combines a fast correlation-based filter (FCBF) and a weighted naive Bayesian model which can identify the most effective items and make accurate quality predictions. Experimental results demonstrate that the proposed method reduces test time by around 2.59% and leads to fewer test escapes compared with the recently adopted test methods. The study shows that the proposed method can effectively reduce the test cost without jeopardizing test quality excessively.

Author(s):  
Matthieu Verdy ◽  
Dominique Morche ◽  
Emeric De Foucauld ◽  
Suzanne Lesecq ◽  
Jean-Pascal Mallet ◽  
...  

2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
Chi-Jih Shih ◽  
Chih-Yao Hsu ◽  
Chun-Yi Kuo ◽  
James Li ◽  
Jiann-Chyi Rau ◽  
...  

Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions:soft-die modeandhard-die mode. The former assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results show that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot reduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die mode to reduce the total test cost for 3D IC.


Author(s):  
Youngkwang Lee ◽  
Young-woo Lee ◽  
Sungyoul Seo ◽  
Sungho Kang

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