scholarly journals A High-Efficiency Low-Power Chip-Based CMOS Liquid Crystal Driver for Tunable Electro-Optic Eyewear

Electronics ◽  
2018 ◽  
Vol 8 (1) ◽  
pp. 14
Author(s):  
Hai Deng ◽  
Guoqiang Li
Keyword(s):  
Liquid Crystal ◽  
Low Power ◽  
High Efficiency ◽  
Charge Pump ◽  
Cmos Technology ◽  
Head Mounted Display ◽  
Vision Correction ◽  
Electro Optic ◽  
Pump Output ◽  
Multi Mode

A high-efficiency low-power chip-based liquid crystal (LC) driver has been successfully designed and implemented for adaptive electro-optic eyewear including tunable vision correction devices (eyeglass, contact lens, intraocular lens, occluder, and prism), phoropter, iris, head-mounted display, and 3D imaging. The driver can generate a 1 kHz bipolar square wave with magnitude tunable from 0 V to 15 V to change the lens focus adaptively. The LC driver output magnitude is controlled by a reference DC voltage that is manually tunable between 0 and 3 V. A multi-mode 1×/2×/3×/4×/5× charge pump is developed for DC-DC conversion to expand the output range with a fast-sink function implemented to regulate the charge pump output. In addition, a new four-phase H-bridge driving scheme is employed to improve the DC/AC inverter efficiency. The LC driver has been successfully implemented and tested as an IC chip (8.6 mm × 8.6 mm) using AMS 0.18 μm High-Voltage CMOS technology.

scholarly journals Low Power AVLS-TSPC based 2/3 Pre-Scaler

2019 ◽  
Vol 9 (1) ◽  
pp. 6687-6693
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Frequency Signal ◽  
High Frequency Signal ◽  
Power Requirement ◽  
Fast Pace ◽  
Integer Division

The technology has grown at an ultra-fast pace along with the world. Small devices with less power and high efficiency are in demand. As the circuit size gets smaller, the power requirement increases due to a greater number of transistors. A pre-scaler is a circuit which reduces the high frequency signal to a low frequency signal by integer division. A new approach to low power pre-scaler is proposed in this paper, which is an add-on to the conventional pre-scaler circuit. A true single-phase clock (TSPC) circuit reduces the skew problems in the clock and is used to realize latches and flip-flops. The objective of low power is fulfilled by incorporating the Adaptive Voltage Level Source (AVLS) to TSPC based circuit. The proposed AVLS-TSPC based pre-scaler was analyzed for a frequency of 10 MHz with a supply voltage of 1.8 V for both divide by 2 and 3 modes. The proposed pre-scaler consumes considerably lesser power when compared to that of the existing pre-scaler circuit. The circuits are implemented in 180 nm CMOS technology using Cadence Virtuoso and simulated using Cadence Spectre.

A high efficiency charge pump circuit for low power applications

2010 ◽  
Vol 31 (1) ◽  
pp. 015009 ◽  
Author(s):  
Feng Peng ◽  
Li Yunlong ◽  
Wu Nanjian
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Charge Pump ◽  
Charge Pump Circuit

LOW-POWER HIGH-SPEED CLASS-AB BUFFER AMPLIFIERS FOR LIQUID-CRYSTAL DISPLAY SIGNAL DRIVER APPLICATION

2002 ◽  
Vol 11 (04) ◽  
pp. 427-444 ◽  
Author(s):  
CHIH-WEN LU
Keyword(s):  
Liquid Crystal ◽  
Low Power ◽  
High Speed ◽  
Dynamic Range ◽  
Liquid Crystal Display ◽  
Stable State ◽  
Cmos Technology ◽  
Output Buffer ◽  
Class Ab ◽  
Input Waveform

Two types of low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer amplifiers which are suitable for the liquid-crystal display signal driver application are proposed. The driving capabilities of the circuits are achieved by adding comparators which sense the rising and falling edges of the input waveform and then turn on an auxiliary driving transistor to help charging/discharging the output load. The auxiliary driving transistors stay at "off" in the stable state, thus drawing no static power. Hence, the buffers draw little current during static but have an improved driving capability during transients. They are demonstrated in a 0.6 μm CMOS technology. The measured data do show that the proposed output buffer circuits are very suitable for the application of liquid-crystal display signal driver.

scholarly journals Charge Pump and Loop Filter for Low Power PLL Using 130nm CMOS Technology

2018 ◽  
Vol 1049 ◽  
pp. 012060
Author(s):  
Nabihah Ahmad ◽  
Nur Atikah Binti Ishaimi ◽  
M. Hairol Jabbar
Keyword(s):  
Low Power ◽  
Charge Pump ◽  
Cmos Technology ◽  
Loop Filter

scholarly journals Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 676
Author(s):  
Labonnah Farzana Rahman ◽  
Mohammad Marufuzzaman ◽  
Lubna Alam ◽  
Mazlin Bin Mokhtar
Keyword(s):  
Low Power ◽  
Radio Frequency Identification ◽  
Output Voltage ◽  
High Efficiency ◽  
Charge Pump ◽  
Design Methods ◽  
Optimization Techniques ◽  
Cmos Process ◽  
Advantages And Disadvantages ◽  
Continuous Power

Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping efficiency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.

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