scholarly journals Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 676
Author(s):  
Labonnah Farzana Rahman ◽  
Mohammad Marufuzzaman ◽  
Lubna Alam ◽  
Mazlin Bin Mokhtar
Keyword(s):  
Low Power ◽  
Radio Frequency Identification ◽  
Output Voltage ◽  
High Efficiency ◽  
Charge Pump ◽  
Design Methods ◽  
Optimization Techniques ◽  
Cmos Process ◽  
Advantages And Disadvantages ◽  
Continuous Power

Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping efficiency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.

Self-Reduction Quiescent Current Low Power Low Dropout Regulator for SoC Application

2012 ◽  
Vol 591-593 ◽  
pp. 2632-2635
Author(s):  
Lee Chu Liang ◽  
Roslina Mohd Sidek
Keyword(s):  
Low Power ◽  
Process Model ◽  
High Efficiency ◽  
System Stability ◽  
Cmos Process ◽  
Output Impedance ◽  
Load Current ◽  
Output Load ◽  
Quiescent Current ◽  
Low Dropout Regulator

A low power low-dropout (LDO) voltage regulator with self-reduction quiescent current is proposed in this paper. This proposed capacitorless LDO for Silicon-on-Chip (SoC) application has introduced a self-adjustable low-impedance circuitry at the output of LDO to attain stability critically during low output load current (less than a few hundred of micro-ampere). When the LDO load current increases, it reduces the LDO output impedance and moved the pole towards higher frequency away from the dominant pole and improving the system stability. When this happen, less amount of quiescent current is needed for the low-impedance circuitry to sustain the low output impedance. In this proposed LDO, the quiescent current that been used to sustain the low output impedance will be self-reduced when the output load current increases. Thus, the reduction of quiescent current at low output load current has tremendously improved the efficiency. The simulation results have shown a promising stability at low load current 0~1mA. The dropout voltage for this LDO is only 100mV at 1.2V supply. The proposed LDO is validated using Silterra 0.13μm CMOS process model and designed with high efficiency at low output load current.

scholarly journals A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes

Sensors ◽  
2019 ◽  
Vol 19 (19) ◽  
pp. 4149
Author(s):  
Xiang Li ◽  
Rui Li ◽  
Chunge Ju ◽  
Bo Hou ◽  
Qi Wei ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Output Voltage ◽  
Charge Pump ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Temperature Changes ◽  
Adjustable Range

Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18- μ m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm 2 . Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at − 40 ∼ 80 ∘ C are less than 1.1%.

scholarly journals Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Electronics ◽  
2016 ◽  
Vol 5 (4) ◽  
pp. 92 ◽  
Author(s):  
Mohammad Badal ◽  
Mamun Reaz ◽  
Zinah Jalil ◽  
Mohammad Bhuiyan
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Shift Register ◽  
Cmos Process ◽  
Flip Flop ◽  
Rfid Tag

A Stable Mode-Selectable Oscillator with Variable Duty Cycle and High-Efficiency

2015 ◽  
Vol 24 (09) ◽  
pp. 1550132 ◽  
Author(s):  
Li-Ye Cheng ◽  
Xin-Quan Lai
Keyword(s):  
Duty Cycle ◽  
High Efficiency ◽  
Dynamic Performance ◽  
Operation Mode ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Process ◽  
Pump Efficiency ◽  
Stable Mode ◽  
Wide Range

A mode-selectable oscillator (OSC) with variable duty cycle for improved charge pump efficiency is proposed in this paper. The novel OSC adjusts its duty cycle according to the operation mode of the charge pump, thus improves the charge-pump efficiency and dynamic performance. The control of variable duty cycle is implemented in digital logic hence it provides robust noise immunity and instantaneous response. The OSC and the charge-pump have been implemented in a 0.6-μm 40-V CMOS process. Experimental results show that the peak efficiency is 92.7% at 200-mA load, the recovery time is less than 25 μs and load transient is 15 mV under 500-mA load variation. The system is able to work under a wide range of input voltage (V IN ) in all modes with low EMI.

A HIGH EFFICIENCY ADAPTIVE CURRENT MODE STEP-UP/STEP-DOWN DC–DC CONVERTER WITH FOUR MODES FOR SMOOTH TRANSITION

2014 ◽  
Vol 23 (07) ◽  
pp. 1450097 ◽  
Author(s):  
YANZHAO MA ◽  
SHAOXI WANG ◽  
SHENGBING ZHANG ◽  
XIAOYA FAN
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
High Efficiency ◽  
Current Mode ◽  
Smooth Transition ◽  
Maximum Efficiency ◽  
Cmos Process ◽  
Voltage Ripple ◽  
Transition Modes ◽  
Step Down

This paper presents a current mode step-up/step-down DC–DC converter with high efficiency, small output voltage ripple, and fast transient response. The control scheme adaptively configures the converter into the proper operation mode. The efficiency is improved by reducing the switching loss, wherein the converter operates like a buck or boost converter, and conduction loss, wherein the average inductor current is reduced in transition modes. The output voltage ripple is significantly reduced by incorporating two constant time transition modes. A fast line transient response is achieved with small overshoot and undershoot voltage. An adaptive substrate selector (ASS) is introduced to dynamically switch the substrate of PMOS power transistors to the highest on-chip voltage. A lossless self-biased current sensor with high-speed and high-accuracy is also achieved. The proposed converter was designed with a standard 0.5 μm CMOS process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V. The maximum load current is 600 mA, and the maximum efficiency is 94%. The output voltage ripple is less than 15 mV in all operation modes.

scholarly journals A 920-MHz Dual-Mode Receiver with Energy Harvesting for UHF RFID Tag and IoT

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1042
Author(s):  
Peiqing Han ◽  
Zhaofeng Zhang ◽  
Yajun Xia ◽  
Niansong Mei
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Radio Frequency Identification ◽  
Supply Voltage ◽  
High Sensitivity ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Dual Mode ◽  
Operating Modes ◽  
On Chip

A low-power dual-mode receiver is presented for ultra-high-frequency (UHF) radio frequency identification (RFID) systems. The reconfigurable architecture of the tag is proposed to be compatible with low-power and high-sensitivity operating modes. The read range of RFID system and the lifetime of the tag are increased by photovoltaic, thermoelectric and RF energy-harvesting topology. The receiver is implemented in a 0.18-μm standard CMOS process and occupies an active area of 0.65 mm × 0.7 mm. For low-power mode, the tag is powered by the rectifier and the sensitivity is −18 dBm. For high-sensitivity mode, the maximum PCE of the fully on-chip energy harvester is 46.5% with over 1-μW output power and the sensitivity is −40 dBm with 880 nW power consumption under the supply voltage of 0.8 V.

A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology

2017 ◽  
Vol 26 (11) ◽  
pp. 1750182
Author(s):  
Indrit Myderrizi ◽  
Ali Zeki
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Output Voltage ◽  
High Speed ◽  
Pulse Signal ◽  
Propagation Delay ◽  
Cmos Process ◽  
Down Low ◽  
Voltage Swing ◽  
Output Voltage Swing

With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.

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