Low Power Testing

2011 ◽  
pp. 395-412
Author(s):  
Zdenek Kotásek ◽  
Jaroslav Škarvada
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Operational Mode ◽  
Dynamic Power ◽  
Low Power Testing ◽  
Test Application ◽  
Basic Concepts ◽  
Power Testing

Portable computer systems and embedded systems are examples of electronic devices which are powered from batteries; therefore, they are designed with the goal of low power consumption. Low power consumption becomes important not only during normal operational mode, but during test application as well when switching activity is higher than in normal mode. In this chapter, a survey of basic concepts and methodologies from the area of low power testing is provided. It is explained here how power consumption is related to switching activities during test application. The concepts of static and dynamic power consumption are discussed together with metrics which can be possibly used to evaluate power consumption. The survey of methods, the goal of which is to reduce dynamic power consumption during test application, is then provided followed by a short survey of power-constrained test scheduling methods.

LOW POWER CONSUMPTION SECURITY PLATFORM FOR INDUSTRIAL COMMUNICATIONS USING AN MPSOC

2013 ◽  
Vol 22 (05) ◽  
pp. 1350029
Author(s):  
JOSE M. GRANADO-CRIADO ◽  
MIGUEL A. VEGA-RODRÍGUEZ ◽  
JOSE M. CHAVES-GONZALEZ ◽  
JUAN M. SANCHEZ-PEREZ ◽  
JUAN A. GOMEZ-PULIDO
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
The Internet ◽  
Secure Protocols ◽  
Industrial Communications

This work presents a novel security platform for industrial communications using a nine-MicroBlaze MPSoC. This platform has low power consumption and cost, therefore, it is very appropriate for embedded systems, where restrictions on cost and power consumption have to be fulfilled. This system uses the RSA asymmetric algorithm combined with the AES symmetric algorithm, which was developed using two encryption modes, ECB and CBC. In this way, the platform makes possible to combine different algorithms and modes in function of the necessities of speed and security required. Furthermore, due to the implementation of standard algorithms (AES and RSA) and modes (ECB and CBC), this platform can be connected to the Internet, and can even use secure protocols as SSL.

scholarly journals A 2048-point Split-Radix Fast Fourier Transform Computed using Radix-4 Butterfly Units

2019 ◽  
Vol 8 (4) ◽  
pp. 2043-2046
Keyword(s):  
Fourier Transform ◽  
Power Consumption ◽  
Low Power ◽  
Fast Fourier Transform ◽  
Fourier Transforms ◽  
Low Power Consumption ◽  
Signal Flow Graph ◽  
Flow Graph ◽  
Dynamic Power ◽  
Fft Algorithms

For the low-power consumption of fast fourier transform, Split-radix fast Fourier transforms are widely used. SRFFT uses less number of mathematical calculations amongst the different FFT algorithms. Split-radix FFT has the same signal flow graph that of conventional radix-2/4 FFT’s. Therefore, the address generation method is same for SRFFT as of radix-2. A low power SRFFT architecture with modified butterfly units is presented over here. Here, it is shown that the, a 2048-point SRFFT is computed using radix-4 butterfly unist. Dynamic power is saved, on compromising the use of extra hardware. Here, the architecture size is increased from radix-2 to 4 and the dynamic power consumption is evaluated.

Optimal design of a high homogeneous and small-size shim coil for atomic spin gyroscope based on 0-1 linear programming

2020 ◽  
Vol 64 (1-4) ◽  
pp. 165-172
Author(s):  
Dongge Deng ◽  
Mingzhi Zhu ◽  
Qiang Shu ◽  
Baoxu Wang ◽  
Fei Yang
Keyword(s):  
Linear Programming ◽  
Power Consumption ◽  
Low Power ◽  
Optimization Design ◽  
Structural Parameters ◽  
Axial Position ◽  
Low Power Consumption ◽  
Optimal Method ◽  
Atomic Spin ◽  
Shim Coil

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Ultra Low Power Consumption for Self-Oscillating Nanoelectromechanical Systems Constructed by Contacting Two Nanowires

Nano Letters ◽  
2013 ◽  
Vol 13 (4) ◽  
pp. 1451-1456 ◽  
Author(s):  
T. Barois ◽  
A. Ayari ◽  
P. Vincent ◽  
S. Perisanu ◽  
P. Poncharal ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Nanoelectromechanical Systems ◽  
Low Power Consumption ◽  
Ultra Low Power

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

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