scholarly journals An FPGA-Based CNN Accelerator Integrating Depthwise Separable Convolution

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 281 ◽  
Author(s):  
Bing Liu ◽  
Danyin Zou ◽  
Lei Feng ◽  
Shou Feng ◽  
Ping Fu ◽  
...  
Keyword(s):  
Graphics Processing Unit ◽  
Processing Unit ◽  
Network Layers ◽  
Ping Pong ◽  
Parameter Configuration ◽  
Field Programmable ◽  
Hardware Resource ◽  
Roofline Model ◽  
On Chip ◽  
Graphics Processing

The Convolutional Neural Network (CNN) has been used in many fields and has achieved remarkable results, such as image classification, face detection, and speech recognition. Compared to GPU (graphics processing unit) and ASIC, a FPGA (field programmable gate array)-based CNN accelerator has great advantages due to its low power consumption and reconfigurable property. However, FPGA’s extremely limited resources and CNN’s huge amount of parameters and computational complexity pose great challenges to the design. Based on the ZYNQ heterogeneous platform and the coordination of resource and bandwidth issues with the roofline model, the CNN accelerator we designed can accelerate both standard convolution and depthwise separable convolution with a high hardware resource rate. The accelerator can handle network layers of different scales through parameter configuration and maximizes bandwidth and achieves full pipelined by using a data stream interface and ping-pong on-chip cache. The experimental results show that the accelerator designed in this paper can achieve 17.11GOPS for 32bit floating point when it can also accelerate depthwise separable convolution, which has obvious advantages compared with other designs.

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

scholarly journals Accelerating Event Detection with DGCNN and FPGAs

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1666
Author(s):  
Zhe Han ◽  
Jingfei Jiang ◽  
Linbo Qiao ◽  
Yong Dou ◽  
Jinwei Xu ◽  
...  
Keyword(s):  
Language Processing ◽  
Event Detection ◽  
Graphics Processing Unit ◽  
Network Size ◽  
Processing Unit ◽  
Sigmoid Function ◽  
Pipelined Architecture ◽  
Proposed Model ◽  
Field Programmable ◽  
Graphics Processing

Recently, Deep Neural Networks (DNNs) have been widely used in natural language processing. However, DNNs are often computation-intensive and memory-expensive. Therefore, deploying DNNs in the real world is very difficult. In order to solve this problem, we proposed a network model based on the dilate gated convolutional neural network, which is very hardware-friendly. We further expanded the word representations and depth of the network to improve the performance of the model. We replaced the Sigmoid function to make it more friendly for hardware computation without loss, and we quantized the network weights and activations to compress the network size. We then proposed the first FPGA (Field Programmable Gate Array)-based event detection accelerator based on the proposed model. The accelerator significantly reduced the latency with the fully pipelined architecture. We implemented the accelerator on the Xilinx XCKU115 FPGA. The experimental results show that our model obtains the highest F1-score of 84.6% in the ACE 2005 corpus. Meanwhile, the accelerator achieved 95.2 giga operations (GOP)/s and 13.4 GOPS/W in performance and energy efficiency, which is 17/158 times higher than the Graphics Processing Unit (GPU).

HIGH PRECISION INTEGER ADDITION, SUBTRACTION AND MULTIPLICATION WITH A GRAPHICS PROCESSING UNIT

2010 ◽  
Vol 20 (04) ◽  
pp. 293-306 ◽  
Author(s):  
NIALL EMMART ◽  
CHARLES WEEMS
Keyword(s):  
High Precision ◽  
Graphics Processing Unit ◽  
Divide And Conquer ◽  
Processing Unit ◽  
Good Potential ◽  
Addition And Subtraction ◽  
Integer Multiplication ◽  
On Chip ◽  
Graphics Processing ◽  
Gpu Architecture

In this paper we evaluate the potential for using an NVIDIA graphics processing unit (GPU) to accelerate high precision integer multiplication, addition, and subtraction. The reported peak vector performance for a typical GPU appears to offer good potential for accelerating such a computation. Because of limitations in the on-chip memory, the high cost of kernel launches, and the nature of the architecture's support for parallelism, we used a hybrid algorithmic approach to obtain good performance on multiplication. On the GPU itself we adapt the Strassen FFT algorithm to multiply 32KB chunks, while on the CPU we adapt the Karatsuba divide-and-conquer approach to optimize application of the GPU's partial multiplies, which are viewed as "digits" by our implementation of Karatsuba. Even with this approach, the result is at best a factor of three increase in performance, compared with using the GMP package on a 64-bit CPU at a comparable technology node. Our implementations of addition and subtraction achieve up to a factor of eight improvement. We identify the issues that limit performance and discuss the likely impact of planned advances in GPU architecture.

scholarly journals ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 838
Author(s):  
Dong Hyun Hwang ◽  
Chang Yeop Han ◽  
Hyun Woo Oh ◽  
Seung Eun Lee
Keyword(s):  
Artificial Intelligence ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Computing Device ◽  
Simulation And Optimization ◽  
Performance Space ◽  
Field Programmable ◽  
Hardware Description ◽  
Graphics Processing

Artificial intelligence algorithms need an external computing device such as a graphics processing unit (GPU) due to computational complexity. For running artificial intelligence algorithms in an embedded device, many studies proposed light-weighted artificial intelligence algorithms and artificial intelligence accelerators. In this paper, we propose the ASimOV framework, which optimizes artificial intelligence algorithms and generates Verilog hardware description language (HDL) code for executing intelligence algorithms in field programmable gate array (FPGA). To verify ASimOV, we explore the performance space of k-NN algorithms and generate Verilog HDL code to demonstrate the k-NN accelerator in FPGA. Our contribution is to provide the artificial intelligence algorithm as an end-to-end pipeline and ensure that it is optimized to a specific dataset through simulation, and an artificial intelligence accelerator is generated in the end.

A GPU-Based Fault Simulator for Small-Delay Faults

2013 ◽  
Vol 753-755 ◽  
pp. 2235-2242
Author(s):  
Ming Ming Peng ◽  
Ji Shun Kuang
Keyword(s):  
Integrated Circuit ◽  
Graphics Processing Unit ◽  
Fault Simulation ◽  
Processing Unit ◽  
Delay Faults ◽  
Clock Frequency ◽  
Simulation Engine ◽  
Small Delay ◽  
On Chip ◽  
Graphics Processing

In this paper, we explore the implementation of fault simulator for small-delay faults on Graphics Processing Unit (GPU). Nowadays the size of integrated circuit is getting smaller and smaller, the clock frequency has become faster and faster, which leads to the effects of small delay fault on chip and is also increasingly obvious. Small delay simulation has become highly important, it is directly related to the accuracy of product and its time to market. At the same time, small delay simulation is a very time consuming process, which requires constantly looking for ways to accelerate the simulation. In recent years, GPU has been used to accelerate the programs of intensive computation in many areas and has achieved very good results. Based on these two points, we consider combining the parallelism of small delay simulation with the high parallel computing ability of GPU to accelerate small delay simulation. Experimental results indicate that our approach is on average 42 when compared to the traditional fault simulation engine.

scholarly journals A Tile-Based EGPU with a Fused Universal Processing Engine and Graphics Coprocessor Cluster

2016 ◽  
Vol 2016 ◽  
pp. 1-9
Author(s):  
Yang Wang ◽  
Li Zhou ◽  
Tao Sun ◽  
Yanhu Chen ◽  
Lei Wang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Graphics Processing Unit ◽  
General Purpose ◽  
Processing Unit ◽  
Clock Frequency ◽  
Embedded Devices ◽  
On Chip ◽  
Graphics Processing ◽  
Graphics Rendering ◽  
Processing Engine

As various applied sensors have been integrated into embedded devices, the Embedded Graphics Processing Unit (EGPU) has assumed more processing tasks, which requires an EGPU with higher performance. A tile-based EGPU is proposed that can be used in both general-purpose computing and 3D graphics rendering. With fused, scalable, and hierarchical parallelism architecture, the EGPU has the ability to address nearly 100 million vertices or fragments and achieves 1 GFLOPS per second at a clock frequency of 200 MHz. A fused and scalable architecture, constituted by Universal Processing Engine (UPE) and Graphics Coprocessor Cluster (GCC), ensures that the EGPU can adapt to various graphic processing scenes and situations, achieving more efficient rendering. Moreover, hierarchical parallelism is implemented via the UPE. Additionally, tiling brings a significant reduction in both system memory bandwidth and power consumption. A 0.18 µm technology library is used for timing and power analysis. The area of the proposed EGPU is 6.5 mm∗6.5 mm, and its power consumption is approximately 349.318 mW. Experimental results demonstrate that the proposed EGPU can be used in a System on Chip (SoC) configuration connected to sensors to accelerate its processing and create a proper balance between performance and cost.

Fast iterative solvers for large compressed-sparse row linear systems on graphics processing unit

2015 ◽  
Vol 10 (1) ◽  
pp. 3-18 ◽  
Author(s):  
Frédéric Magoulès ◽  
Abal-Kassim Cheik Ahamed ◽  
Roman Putanowicz
Keyword(s):  
Linear Systems ◽  
Graphics Processing Unit ◽  
Iterative Solvers ◽  
Processing Unit ◽  
Compressed Sparse Row ◽  
Graphics Processing

Implementing wide baseline matching algorithms on a graphics processing unit.

2007 ◽  
Author(s):  
Fredrick H. Rothganger ◽  
Kurt W. Larson ◽  
Antonio Ignacio Gonzales ◽  
Daniel S. Myers
Keyword(s):  
Graphics Processing Unit ◽  
Processing Unit ◽  
Wide Baseline Matching ◽  
Graphics Processing

scholarly journals Two Decades of 4D-QSAR: A Dying Art or Staging a Comeback?

2021 ◽  
Vol 22 (10) ◽  
pp. 5212
Author(s):  
Andrzej Bak
Keyword(s):  
Molecular Conformation ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Diverse Range ◽  
Current State ◽  
Gpu Clusters ◽  
Pharmacophore Hypothesis ◽  
Rising Power ◽  
Graphics Processing ◽  
Ligand Conformation

A key question confronting computational chemists concerns the preferable ligand geometry that fits complementarily into the receptor pocket. Typically, the postulated ‘bioactive’ 3D ligand conformation is constructed as a ‘sophisticated guess’ (unnecessarily geometry-optimized) mirroring the pharmacophore hypothesis—sometimes based on an erroneous prerequisite. Hence, 4D-QSAR scheme and its ‘dialects’ have been practically implemented as higher level of model abstraction that allows the examination of the multiple molecular conformation, orientation and protonation representation, respectively. Nearly a quarter of a century has passed since the eminent work of Hopfinger appeared on the stage; therefore the natural question occurs whether 4D-QSAR approach is still appealing to the scientific community? With no intention to be comprehensive, a review of the current state of art in the field of receptor-independent (RI) and receptor-dependent (RD) 4D-QSAR methodology is provided with a brief examination of the ‘mainstream’ algorithms. In fact, a myriad of 4D-QSAR methods have been implemented and applied practically for a diverse range of molecules. It seems that, 4D-QSAR approach has been experiencing a promising renaissance of interests that might be fuelled by the rising power of the graphics processing unit (GPU) clusters applied to full-atom MD-based simulations of the protein-ligand complexes.

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