scholarly journals How Europe Is Preparing Its Core Solution for Exascale Machines and a Global, Sovereign, Advanced Computing Platform

2020 ◽  
Vol 25 (3) ◽  
pp. 46 ◽  
Author(s):  
Mario Kovač ◽  
Philippe Notton ◽  
Daniel Hofman ◽  
Josip Knezović
Keyword(s):  
High Performance ◽  
Embedded Software ◽  
Economic Viability ◽  
Computing Platform ◽  
Systems On Chip ◽  
The World ◽  
Core Solution ◽  
On Chip ◽  
Advanced Computing ◽  
Performance Computing

In this paper, we present an overview of the European Processor Initiative (EPI), one of the cornerstones of the EuroHPC Joint Undertaking, a new European Union strategic entity focused on pooling the Union’s and national resources on HPC to acquire, build and deploy the most powerful supercomputers in the world within Europe. EPI started its activities in December 2018. The first three years drew processor and platform designers, embedded software, middleware, applications and usage experts from 10 EU countries together to co-design Europe’s first HPC Systems on Chip and accelerators with its unique Common Platform (CP) technology. One of EPI’s core activities also takes place in the automotive sector, providing architectural solutions for a novel embedded high-performance computing (eHPC) platform and ensuring the overall economic viability of the initiative.

МЕТОДЫ ДОСТИЖЕНИЯ МАКСИМАЛЬНОЙ ЭФФЕКТИВНОСТИ ПЛАТФОРМЫ ПРОТОТИПИРОВАНИЯ ВЫСОКОПРОИЗВОДИТЕЛЬНЫХ СИСТЕМ НА КРИСТАЛЛЕ НА ЗАДАЧАХ ИСКУССТВЕННОГО ИНТЕЛЛЕКТА

2020 ◽  
Vol 96 (3s) ◽  
pp. 585-588
Author(s):  
С.Е. Фролова ◽  
Е.С. Янакова
Keyword(s):  
Neural Network ◽  
Artificial Intelligence ◽  
Computer Vision ◽  
High Performance ◽  
Systems On Chip ◽  
High Performance Systems ◽  
On Chip ◽  
Network Technologies ◽  
Neural Network Technologies

Предлагаются методы построения платформ прототипирования высокопроизводительных систем на кристалле для задач искусственного интеллекта. Изложены требования к платформам подобного класса и принципы изменения проекта СнК для имплементации в прототип. Рассматриваются методы отладки проектов на платформе прототипирования. Приведены результаты работ алгоритмов компьютерного зрения с использованием нейросетевых технологий на FPGA-прототипе семантических ядер ELcore. Methods have been proposed for building prototyping platforms for high-performance systems-on-chip for artificial intelligence tasks. The requirements for platforms of this class and the principles for changing the design of the SoC for implementation in the prototype have been described as well as methods of debugging projects on the prototyping platform. The results of the work of computer vision algorithms using neural network technologies on the FPGA prototype of the ELcore semantic cores have been presented.

scholarly journals Location of Processor Allocator and Job Scheduler and Its Impact on CMP Performance

2012 ◽  
Vol 58 (1) ◽  
pp. 9-14 ◽  
Author(s):  
Dawid Zydek ◽  
Grzegorz Chmaj ◽  
Alaa Shawky ◽  
Henry Selvaraj
Keyword(s):  
High Performance ◽  
Chip Multiprocessors ◽  
Energy Savings ◽  
Processor Allocation ◽  
Processing Elements ◽  
Energy Models ◽  
Allocation Process ◽  
On Chip ◽  
Job Scheduler ◽  
Performance Computing

Location of Processor Allocator and Job Scheduler and Its Impact on CMP PerformanceHigh Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and JS, and processing elements. We present energy models for the researched CMP components, mathematical model of the system, and experimentation system. Based on experimental results, proper placement of PA and JS on a chip can provide up to 45% NoC energy savings.

scholarly journals Special Issue on Automatic Application Tuning for HPC Architectures

2014 ◽  
Vol 22 (4) ◽  
pp. 259-260 ◽  
Author(s):  
Siegfried Benkner ◽  
Franz Franchetti ◽  
Hans Michael Gerndt ◽  
Jeffrey K. Hollingsworth
Keyword(s):  
High Performance ◽  
Research Field ◽  
Performance Tuning ◽  
Full Potential ◽  
Research Groups ◽  
Special Issue ◽  
The World ◽  
And Performance ◽  
Application Tuning ◽  
Performance Computing

High Performance Computing architectures have become incredibly complex and exploiting their full potential is becoming more and more challenging. As a consequence, automatic performance tuning (autotuning) of HPC applications is of growing interest and many research groups around the world are currently involved. Autotuning is still a rapidly evolving research field with many different approaches being taken. This special issue features selected papers presented at the Dagstuhl seminar on “Automatic Application Tuning for HPC Architectures” in October 2013, which brought together researchers from the areas of autotuning and performance analysis in order to exchange ideas and steer future collaborations.

scholarly journals CONTENT OF A SPECIAL COURSE ON HIGH PERFORMANCE COMPUTING

2020 ◽  
Vol 71 (3) ◽  
pp. 263-267
Author(s):  
М. Serik ◽  
◽  
G. Zh. Yerlanova ◽  
Keyword(s):  
Information Technology ◽  
High Performance Computing ◽  
Computer Technology ◽  
High Performance ◽  
Practical Importance ◽  
Modern Society ◽  
Educational Process ◽  
Dynamic Development ◽  
The World ◽  
Performance Computing

At present, along with the dynamic development of computer technology in the world, the most effective ways of solving problems of practical importance are being considered. High performance computing takes the lead in this. Therefore, the development of modern society is closely related to the training of experienced, modern specialists in the field of information technology. This, in turn, depends on the inclusion of new courses in the curriculum and full coverage of these issues in the content of the taught courses. This article analyzes the courses on high performance computing, taught at experimental bases and abroad, on the basis of this, the topics of the special course and the content recommended for implementation in the educational process are determined. During the training, the competencies of students in high performance computing were identified.

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