scholarly journals Investigation on Ambipolar Current Suppression Using a Stacked Gate in an L-shaped Tunnel Field-Effect Transistor

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 753
Author(s):  
Junsu Yu ◽  
Sihyun Kim ◽  
Donghyun Ryu ◽  
Kitae Lee ◽  
Changha Kim ◽  
...  

L-shaped tunnel field-effect transistor (TFET) provides higher on-current than a conventional TFET through band-to-band tunneling in the vertical direction of the channel. However, L-shaped TFET is disadvantageous for low-power applications because of increased off-current due to the large ambipolar current. In this paper, a stacked gate L-shaped TFET is proposed for suppression of ambipolar current. Stacked gates can be easily implemented using the structural features of L-shaped TFET, and on- and off-current can be controlled separately by using different gates located near the source and the drain, respectively. As a result, the suppression of ambipolarity is observed with respect to work function difference between two gates by simulation of the band-to-band tunneling generation. Furthermore, the proposed device suppresses ambipolar current better than existing ambipolar current suppression methods. In particular, low drain resistance is achieved as there is no need to reduce drain doping, which leads to a 7% enhanced on-current. Finally, we present the fabrication method for a stacked gate L-shaped TFET.

2017 ◽  
Vol 122 (1) ◽  
pp. 014502 ◽  
Author(s):  
Prateek Jain ◽  
Priyank Rastogi ◽  
Chandan Yadav ◽  
Amit Agarwal ◽  
Yogesh Singh Chauhan

Tunnel Field Effect Transistor (TFET) is gated reverse biased P-I-N diode structured semiconductor device and can be considered as a reliable low power device. TCAD (Sentaurus 2D) simulations for various Gate metal work function (4.1-4.3 eV) shows that its ON-current (ION) arises from quantum mechanical band-to-band tunneling (B2BT) and observed that threshold Voltage (VT) for TFET decreases with increase in Gate metal work function. The thermionic emission of electrons in MOSFET limits the sub-threshold swing (SS) by 60 mV/dec whereas TFET has potential for low SS ie. SS<60 mV/dec. TCAD Simulations confirmed that that the Gate – Drain capacitance (Cgd) strongly follows the Gate capacitance (Cgg) all over the voltage range (0-0.9V) which increases the miller capacitance for TFET. It is investigated that for TFET, the injection of carriers into the channel is through B2BT which effectively couples the Gate charge to the Drain. A look up table based Verilog-A model is generated for TFET and used to simulate the static and dynamic behavior of TFET based digital circuit in Cadence spectre. Miller effect causes the peak voltage overshoots are noticed at the drain side during transient responses and can be responsible for dynamic power loss and high turn ON/OFF delay


Author(s):  
Ajay Kumar Singh ◽  
Tan Chun Fui

Background: Power reduction is a severe design concern for submicron logic circuits, which can be achieved by scaling the supply voltage. Modern Field Effect Transistor (FET) circuits require at least 60 mV of gate voltage for a better current drive at room temperature. The tunnel Field Effect Transistor (TFET) is a leading future device due to its steep subthreshold swing (SS), making its ideal device at a low power supply. Steep switching TFET can extend the supply voltage scaling with improved energy efficiency for digital and analog applications. These devices suffer from a sizeable ambipolar current, which cannot be reduced using Dual Metal Gate (DMG) alone. Gate dielectric materials play a crucial role in suppressing the ambipolar current. Objective: This paper presents a new structure known as triple-gate-dielectric (DM_TGD) TFET, which combines the dielectric and work function engineering to solve these problems. Method: The proposed structure uses DMG with three dielectric gate materials titanium oxide (TiO2), aluminum oxide (Al2O3), and silicon dioxide (SiO2). The high dielectric material alone as gate oxide increases the fringing fields, which results in higher gate capacitance. This structure has been simulated using 2-D ATLAS simulator in terms of drive current (Ion), ambipolar current (Iamb) and transconductance (gm). Results: The device offers better gm, lower SS, lower leakage and larger drive currents due to weaker insulating barriers at the tunneling junction. Also, higher effective dielectric constant gives better gate coupling and lower trap density. Conclusion: The proposed structure suppresses the ambipolar current and enhance the drive current with reduced SCEs.


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