Numerical Optimization of a Fully Cross-Coupled Rectifier Circuit for Wireless Passive Ultra Low Power Sensor Nodes

In the context of the Internet of Things, billions of devices—especially sensors—will be linked together in the next few years. A core component of wireless passive sensor nodes is the rectifier, which has to provide the circuit with sufficient operating voltage. In these devices, the rectifier has to be as energy efficient as possible in order to guarantee an optimal operation. Therefore, a numerical optimization scheme is proposed in this paper, which is able to find a unique optimal solution for an integrated Complementary Metal-Oxide-Semiconductor (CMOS) rectifier circuit with Self-Vth-Cancellation (SVC). An exploration of the parameter space is carried out in order to generate a meaningful target function for enhancing the rectified power for a fixed communication distance. In this paper, a mean conversion efficiency is introduced, which is a more valid target function for optimization than the Voltage Conversion Efficiency (VCE) and the commonly used Power Conversion Efficiency (PCE) and is defined as the arithmetic mean between PCE and VCE. Various trade-offs between output voltage, PCE, VCE and MCE are shown, which provide valuable information for low power rectifier designs. With the proposed method, a rectifier in a low power 55 nm process from Globalfoundries (GF55LPe) is optimized and simulated at −30 dBm input power. A mean PCE of 63.33% and a mean VCE of 63.40% is achieved.

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Ultra-low-power sensor nodes featuring a virtual runtime environment

2012 IEEE International Conference on Communications (ICC) ◽

10.1109/icc.2012.6364704 ◽

2012 ◽

Author(s):

Emanuele Lattanzi ◽

Alessandro Bogliolo

Keyword(s):

Low Power ◽

Sensor Nodes ◽

Ultra Low Power ◽

Runtime Environment ◽

Power Sensor

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Exploiting ultra-low-power ultrasonic wake-up triggering for sensor nodes distance measurements

Proceedings of the 11th ACM Conference on Embedded Networked Sensor Systems - SenSys '13 ◽

10.1145/2517351.2517375 ◽

2013 ◽

Author(s):

Emanuele Lattanzi ◽

Matteo Dromedari ◽

Valerio Freschi ◽

Andrea Seraghiti ◽

Alessandro Bogliolo

Keyword(s):

Low Power ◽

Sensor Nodes ◽

Distance Measurements ◽

Ultra Low Power ◽

Power Ultrasonic

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A 28.1GHz ultra-low-power SHM with AC-DC spliting LC-tank and an analysis of the switch-conversion efficiency

2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN) ◽

10.1109/iccsn.2017.8230362 ◽

2017 ◽

Author(s):

Liming Wang ◽

Toshihiko Yoshimasu

Keyword(s):

Low Power ◽

Conversion Efficiency ◽

Ultra Low Power ◽

Lc Tank

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Circuits for ultra-low power millimeter-scale sensor nodes

2012 Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR) ◽

10.1109/acssc.2012.6489113 ◽

2012 ◽

Cited By ~ 1

Author(s):

Yoonmyung Lee ◽

Dennis Sylvester ◽

David Blaauw

Keyword(s):

Low Power ◽

Sensor Nodes ◽

Ultra Low Power

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An ultra-low-power power management IC for energy-scavenged Wireless Sensor Nodes

2008 IEEE Power Electronics Specialists Conference ◽

10.1109/pesc.2008.4592048 ◽

2008 ◽

Cited By ~ 47

Author(s):

Michael D. Seeman ◽

Seth R. Sanders ◽

Jan M. Rabaey

Keyword(s):

Low Power ◽

Power Management ◽

Sensor Nodes ◽

Wireless Sensor ◽

Wireless Sensor Nodes ◽

Ultra Low Power ◽

Power Management Ic

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A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications

Electronics ◽

10.3390/electronics9060928 ◽

2020 ◽

Vol 9 (6) ◽

pp. 928 ◽

Cited By ~ 1

Author(s):

Taehoon Kim ◽

Sivasundar Manisankar ◽

Yeonbae Chung

Keyword(s):

Low Power ◽

Low Voltage ◽

Cost Effective ◽

Operating Mode ◽

Sleep Mode ◽

Cmos Process ◽

Operating Voltage ◽

Cross Point ◽

Ultra Low Power ◽

Static Ram

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.

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