scholarly journals Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6079
Author(s):  
Shunsuke Okura ◽  
Masanori Aoki ◽  
Tatsuya Oyama ◽  
Masayoshi Shirahata ◽  
Takeshi Fujino ◽  
...  

In order to realize image information security starting from the data source, challenge–response (CR) device authentication, based on a Physically Unclonable Function (PUF) with a 2 Mpixel CMOS image sensor (CIS), is studied, in which variation of the transistor in the pixel array is utilized. As each CR pair can be used only once to make the CIS PUF resistant to the modeling attack, CR authentication with CIS can be carried out 4050 times, with basic post-processing to generate the PUF ID. If a larger number of authentications is required, advanced post-processing using Lehmer encoding can be utilized to carry out authentication 14,858 times. According to the PUF performance evaluation, the authentication error rate is less than 0.001 ppm. Furthermore, the area overhead of the CIS chip for the basic and advanced post-processing is only 1% and 2%, respectively, based on a Verilog HDL model circuit design.

2020 ◽  
Vol 10 (11) ◽  
pp. 2745-2753
Author(s):  
Jimin Cheon ◽  
Dongmyung Lee ◽  
Hojong Choi

An active pixel sensor (APS) in a digital X-ray detector is the dominant circuitry for a CMOS image sensor (CIS) despite its lower fill factor (FF) compared to that of a passive pixel sensor (PPS). Although the PPS provides higher FF, its overall signal-to-noise ratio (SNR) is lower than that of the APS. The required high resolution and small focal plane can be achieved by reducing the number of transistors and contacts per pixel. We proposed a novel passive pixel array and a high precision current amplifier to improve the dynamic range (DR) without minimizing the sensitivity for diagnostic compact digital X-ray detector applications. The PPS can be an alternative to improve the FF. However, size reduction of the feedback capacitor causes degradation of SNR performance. This paper proposes a novel PPS based on readout and amplification circuits with a high precision current amplifier to minimize performance degradation. The expected result was attained with a 0.35-μm CMOS process parameter with power supply voltage of 3.3 V. The proposed PPS has a saturation signal of 1.5 V, dynamic range of 63.5 dB, and total power consumption of 13.47 mW. Therefore, the proposed PPS readout circuit improves the dynamic range without sacrificing the sensitivity.


2011 ◽  
Vol 216 ◽  
pp. 29-33
Author(s):  
Lei Xu ◽  
Wei Lu

In order to meet real-time and quick requirements for video information acquiring and processing, this paper introduces a hardware platform based on Altera's Cyclone series EP1C12Q240C8, to descript the driving timing for CMOS image sensor OV7620 with Verilog HDL language to acquire video information. The system uses SCCB programming model, establishes communication between FPGA chip and CMOS image sensor to achieve the control and acquisition of the signal. In order to achieve operational requirements in different environments and needs, the corresponding registers and the controller are set within CMOS image sensor. Experimental results show that the control of the CMOS image sensor OV7620 flexibly provides a stable and reliable source of raw information for video monitor, industrial applications such as on-site monitoring.


2015 ◽  
Author(s):  
Fengmei Cao ◽  
Shengyu Song ◽  
Tingzhu Bai ◽  
Nan Cao

2004 ◽  
Author(s):  
Omar M. Elkhalili ◽  
Olaf Schrey ◽  
Ralf F. Jeremias ◽  
Peter Mengel ◽  
Martin Petermann ◽  
...  

2000 ◽  
Author(s):  
Wenru Zhang ◽  
Suntao Wu ◽  
Donghui Guo ◽  
Gerard Parr

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  

2020 ◽  
Vol 2020 (7) ◽  
pp. 143-1-143-6 ◽  
Author(s):  
Yasuyuki Fujihara ◽  
Maasa Murata ◽  
Shota Nakayama ◽  
Rihito Kuroda ◽  
Shigetoshi Sugawa

This paper presents a prototype linear response single exposure CMOS image sensor with two-stage lateral overflow integration trench capacitors (LOFITreCs) exhibiting over 120dB dynamic range with 11.4Me- full well capacity (FWC) and maximum signal-to-noise ratio (SNR) of 70dB. The measured SNR at all switching points were over 35dB thanks to the proposed two-stage LOFITreCs.


Author(s):  
Benedict Drevniok ◽  
St. John Dixon-Warren ◽  
Oskar Amster ◽  
Stuart L Friedman ◽  
Yongliang Yang

Abstract Scanning microwave impedance microscopy was used to analyze a CMOS image sensor sample to reveal details of the dopant profiling in planar and cross-sectional samples. Sitespecific capacitance-voltage spectroscopy was performed on different regions of the samples.


2014 ◽  
Vol 35 (3) ◽  
pp. 035005 ◽  
Author(s):  
Kaiming Nie ◽  
Suying Yao ◽  
Jiangtao Xu ◽  
Zhaorui Jiang

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