scholarly journals Energy Performance Analysis and Modelling of LoRa Prototyping Boards

Sensors ◽  
2021 ◽  
Vol 21 (23) ◽  
pp. 7992
Author(s):  
Solomon Ould ◽  
Nick S. Bennett

LoRaWAN has gained significant attention for Internet-of-Things (IOT) applications due to its low power consumption and long range potential for data transmission. While there is a significant body of work assessing LoRA coverage and data transmission characteristics, there is a lack of data available about commercially available LoRa prototyping boards and their power consumption, in relation to their features. It is currently difficult to estimate the power consumption of a LoRa module operating under different transmission profiles, due to a lack of manufacturer data available. In this study, power testing has been carried out on physical hardware and significant variation was found in the power consumption of competing boards, all marketed as “extremely low power”. In this paper, testing results are presented alongside an experimentally-derived power model for the lowest power LoRa module, and power requirements are compared to firmware settings. The power analysis adds to existing work showing trends in data-rate and transmission power settings effects on electrical power consumption. The model’s accuracy is experimentally verified and shows acceptable agreement to estimated values. Finally, applications for the model are presented by way of a hypothetical scenario and calculations performed in order to estimate battery life and energy consumption for varying data transmission intervals.

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.


2021 ◽  
Author(s):  
Valerio Vitali ◽  
Hao Liu ◽  
Iosif Demirtzioglou ◽  
Cosimo Lacava ◽  
Kyle R. H. Bottrill ◽  
...  

2015 ◽  
Vol 76 ◽  
pp. 302-307 ◽  
Author(s):  
Aina Mardhiyah M. Ghazali ◽  
W.Z.W. Hasan ◽  
M.N. Hamidun ◽  
Ahmed H. Sabry ◽  
S.A. Ahmed ◽  
...  

2013 ◽  
Vol 416-417 ◽  
pp. 900-903 ◽  
Author(s):  
Yu Hang Jiang ◽  
Hong Xia Yang

Zigbee technology is a kind of bi-directional wireless communication technology characterized by close distance, low complexity, low power consumption, low speed and low cost. It is mainly used for data transmission of various electronic equipments with short distance, low power consumption and low transmission speed, as well as application of typical periodic data, intermittent data and low reaction time data transmission. This thesis first of all makes an analysis of characteristics of zigbee technology, based on which the design of wireless intelligent home control system based on zigbee technology is proposed. Finally, it gives an analysis of the daily management and maintenance of intelligent system, so as to contribute to further studies.


2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.


Sign in / Sign up

Export Citation Format

Share Document