Algorithm for Clustering the Moduli of RNS for the Application of Optimization of Time Complexity in Standard Cipher System

Residue number system (RNS) has emerged as a knocking field of research due to its high speed, fault tolerant, carry free and parallel characteristics. Due to these features it has got important role in high performance computing especially with reduced delay. There are various algorithms have been found as a result of the research with respect to RNS. Additionally, since RNS reduces word length due to the modular operations, its computations are faster compared to binary computations. But the major challenges are the selection of moduli sets for the forward (decimal to residue numbers) and reverse (residue numbers to decimal) conversion. RNS performance is purely depending on how efficiently an algorithm computes / chooses the moduli sets [1]-[6]. This paper proposes new method for selecting the moduli sets and its usage in cryptographic applications based on Schonhage modular factorization. The paper proposes six moduli sets {6qk1, 6qk+1, 6qk+3, 6qk+5, 6qk+7, 6qk+11} for the RNS conversions but the Schonhage moduli sets are expressed as the exponents that creates a large gap between the moduli’s computed. Hence, a new method is proposed to for computing moduli sets that helps in representing all the decomposed values approximately in the same range.

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A MEMORYLESS REVERSE CONVERTER FOR THE 4-MODULI SUPERSET {2n - 1, 2n, 2n + 1, 2n + 1 - 1}

Journal of Circuits System and Computers ◽

10.1142/s0218126600000044 ◽

2000 ◽

Vol 10 (01n02) ◽

pp. 85-99 ◽

Cited By ~ 37

Author(s):

A. P VINOD ◽

A. BENJAMIN PREMKUMAR

Keyword(s):

High Performance ◽

Dynamic Range ◽

Number System ◽

Residue Number System ◽

Main Challenge ◽

Reverse Converter ◽

Residue Number ◽

Compensation Technique ◽

The Common ◽

Performance Computing

This paper presents a residue number system to binary converter in the four moduli set {2n - 1, 2n, 2n + 1, 2n + 1 - 1}, valid for even values of n. This moduli set is an extension of the popular set {2n - 1, 2n + 1}. The number theoretic properties of the moduli set of the form 2n ± 1 are exploited to design the converter. The main challenge of dealing with fractions in Residue Number System is overcome by using the fraction compensation technique. A hardware implementation using only adders is also proposed. When compared to the common three moduli reverse converters, this four moduli converter offers a larger dynamic range and higher parallelism, which makes it useful for high performance computing.

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An overview of high-performance computing using the residue number system

Program systems theory and applications ◽

10.25209/2079-3316-2021-12-2-137-192 ◽

2021 ◽

Vol 12 (2) ◽

pp. 137-192

Author(s):

Константин Сергеевич Исупов

Keyword(s):

High Performance Computing ◽

High Performance ◽

Number System ◽

Residue Number System ◽

Residue Number ◽

Performance Computing

Система остаточных классов (СОК) — это непозиционная система счисления, являющаяся альтернативой двоичному представлению чисел. В СОК большое целое число представляется в виде набора меньших чисел, являющихся остатками от деления исходной величины на выбранные модули. СОК выполняет сложение, вычитание и умножение с каждым остатком по отдельности. Это приводит к параллельной, свободной от переносов и высокоскоростной компьютерной арифметике для высокопроизводительных вычислений. Однако немодульные операции, требующие оценки величины числа по остаткам, являются сложными для реализации в СОК, так как для них не существует параллельной формы. В вопросах практического использования СОК выполнение немодульных операций занимает центральное место. Представлен обзор исследований в области разработки и применения на практике методов высокопроизводительных вычислений на основе СОК: Рассмотрены существующие техники выполнения важнейших немодульных операций, таких как обратное преобразование, сравнение чисел, вычисление знака и деление. Акцент сделан на методы, пригодные для произвольных наборов модулей. Показано, каким образом арифметика на основе СОК находит практическое применение в облачных средах, блокчейн-технологиях, вычислениях многократной точности и глубоких нейронных сетях. Рассмотрена новая программная библиотека высокопроизводительных вычислений в СОК для CPU и GPU, которая может быть полезной для задач, требующих больших динамических диапазонов (сотни и тысячи бит). Обзор ориентирован на развитие новых направлений исследований, посвященных применению непозиционных систем счисления с параллельной структурой в ресурсоемких приложениях.

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HDL Implementation of Five Moduli Residue Number System

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.i7768.078919 ◽

2019 ◽

Vol 8 (9) ◽

pp. 689-693

Keyword(s):

High Speed ◽

Fault Tolerant ◽

Number System ◽

Residue Number System ◽

Verilog Hdl ◽

Forward Converter ◽

Half Adder ◽

Ripple Carry Adder ◽

Residue Number ◽

Day By Day

The demand for residue number system (RNS) is increasing day by day because of its high speed and fault tolerant characteristics. RNS encodes a large number into group of small numbers, which consequently increases the overall data processing rate. This paper presents an analysis of the forward converter designed using ripple carry adder (RCA), carry save adder (CSA), and half adder-like (HAL), for the figure of merits area, delay, and power for five moduli set: 2n -1, 2n , 2n +1, 2n+1 -1, and 2n-1 -1 with the standard cells at 90 nm technology. The designing of different blocks has been done in Verilog-HDL. The area, delay, and power of the implemented circuits are obtained using the Synopsys Design Compiler at 90 nm technology node, while VCS is used for verification. It is observed that the area of the architecture using CSA is less, whereas power utilization and timing behavior are better in HAL.

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Optimized Parity-Based Error Detection and Correction Methods for Residue Number System

Journal of Circuits System and Computers ◽

10.1142/s0218126619500026 ◽

2018 ◽

Vol 28 (01) ◽

pp. 1950002 ◽

Cited By ~ 1

Author(s):

Adib Armand ◽

Somayeh Timarchi ◽

Hossein Mahdavi

Keyword(s):

Fault Tolerance ◽

Error Detection ◽

High Speed ◽

Fault Tolerant ◽

Number System ◽

Low Complexity ◽

Residue Number System ◽

Cell Library ◽

Error Detection And Correction ◽

Residue Number

Residue Number System (RNS) has been extensively used in high-speed applications. It inherits the advantages of parallelism and modularity, which lead to fault tolerance property. Since carry propagation is limited to each module in RNS, errors do not propagate inter-moduli. Indeed, due to the restriction in carry propagation and fault tolerance property, RNS can be promisingly fast and reliable that makes it a favorable encoding for the digital systems which are highly prone to noise like communication channels. By adding some extra moduli, the so-called redundant RNS (RRNS) is gained. Although several methods around RRNS have already been proposed in the literature, the structures without need for extra moduli have not been introduced yet. This paper addresses three Error Detection and Correction (EDC) schemes for RNS based on parity structures. Using these techniques, the low power fault-tolerant RNS methods with low complexity are presented. Synthesis results using 180[Formula: see text]nm CMOS standard cell library show that the proposed architectures for the three-moduli set [Formula: see text] are in average 17%, 52% and 44% more efficient than the conventional RRNS in terms of delay, power consumption, and area overhead, respectively, without losing the EDC capability.

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Constant-coefficient FIR filters based on residue number system arithmetic

Serbian Journal of Electrical Engineering ◽

10.2298/sjee1203325s ◽

2012 ◽

Vol 9 (3) ◽

pp. 325-342 ◽

Cited By ~ 1

Author(s):

Negovan Stamenkovic ◽

Vladica Stojanovic

Keyword(s):

Power Dissipation ◽

High Speed ◽

Finite Impulse Response ◽

Number System ◽

Residue Number System ◽

Fir Filter ◽

Fir Filters ◽

Residue Number ◽

Low Power Dissipation ◽

Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

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