A MEMORYLESS REVERSE CONVERTER FOR THE 4-MODULI SUPERSET {2n - 1, 2n, 2n + 1, 2n + 1 - 1}

2000 ◽  
Vol 10 (01n02) ◽  
pp. 85-99 ◽  
Author(s):  
A. P VINOD ◽  
A. BENJAMIN PREMKUMAR
Keyword(s):  
High Performance ◽  
Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
Main Challenge ◽  
Reverse Converter ◽  
Residue Number ◽  
Compensation Technique ◽  
The Common ◽  
Performance Computing

This paper presents a residue number system to binary converter in the four moduli set {2n - 1, 2n, 2n + 1, 2n + 1 - 1}, valid for even values of n. This moduli set is an extension of the popular set {2n - 1, 2n + 1}. The number theoretic properties of the moduli set of the form 2n ± 1 are exploited to design the converter. The main challenge of dealing with fractions in Residue Number System is overcome by using the fraction compensation technique. A hardware implementation using only adders is also proposed. When compared to the common three moduli reverse converters, this four moduli converter offers a larger dynamic range and higher parallelism, which makes it useful for high performance computing.

scholarly journals An overview of high-performance computing using the residue number system

2021 ◽  
Vol 12 (2) ◽  
pp. 137-192
Author(s):  
Константин Сергеевич Исупов
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
Number System ◽  
Residue Number System ◽  
Residue Number ◽  
Performance Computing

Система остаточных классов (СОК) — это непозиционная система счисления, являющаяся альтернативой двоичному представлению чисел. В СОК большое целое число представляется в виде набора меньших чисел, являющихся остатками от деления исходной величины на выбранные модули. СОК выполняет сложение, вычитание и умножение с каждым остатком по отдельности. Это приводит к параллельной, свободной от переносов и высокоскоростной компьютерной арифметике для высокопроизводительных вычислений. Однако немодульные операции, требующие оценки величины числа по остаткам, являются сложными для реализации в СОК, так как для них не существует параллельной формы. В вопросах практического использования СОК выполнение немодульных операций занимает центральное место. Представлен обзор исследований в области разработки и применения на практике методов высокопроизводительных вычислений на основе СОК: Рассмотрены существующие техники выполнения важнейших немодульных операций, таких как обратное преобразование, сравнение чисел, вычисление знака и деление. Акцент сделан на методы, пригодные для произвольных наборов модулей. Показано, каким образом арифметика на основе СОК находит практическое применение в облачных средах, блокчейн-технологиях, вычислениях многократной точности и глубоких нейронных сетях. Рассмотрена новая программная библиотека высокопроизводительных вычислений в СОК для CPU и GPU, которая может быть полезной для задач, требующих больших динамических диапазонов (сотни и тысячи бит). Обзор ориентирован на развитие новых направлений исследований, посвященных применению непозиционных систем счисления с параллельной структурой в ресурсоемких приложениях.

scholarly journals High-Performance Computation in Residue Number System Using Floating-Point Arithmetic

Computation ◽  
2021 ◽  
Vol 9 (2) ◽  
pp. 9
Author(s):  
Konstantin Isupov
Keyword(s):  
Graphics Processing Units ◽  
High Performance ◽  
Dynamic Range ◽  
Practical Interest ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Mixed Radix Conversion ◽  
Multiple Precision ◽  
Residue Number

Residue number system (RNS) is known for its parallel arithmetic and has been used in recent decades in various important applications, from digital signal processing and deep neural networks to cryptography and high-precision computation. However, comparison, sign identification, overflow detection, and division are still hard to implement in RNS. For such operations, most of the methods proposed in the literature only support small dynamic ranges (up to several tens of bits), so they are only suitable for low-precision applications. We recently proposed a method that supports arbitrary moduli sets with cryptographically sized dynamic ranges, up to several thousands of bits. The practical interest of our method compared to existing methods is that it relies only on very fast standard floating-point operations, so it is suitable for multiple-precision applications and can be efficiently implemented on many general-purpose platforms that support IEEE 754 arithmetic. In this paper, we make further improvements to this method and demonstrate that it can successfully be applied to implement efficient data-parallel primitives operating in the RNS domain, namely finding the maximum element of an array of RNS numbers on graphics processing units. Our experimental results on an NVIDIA RTX 2080 GPU show that for random residues and a 128-moduli set with 2048-bit dynamic range, the proposed implementation reduces the running time by a factor of 39 and the memory consumption by a factor of 13 compared to an implementation based on mixed-radix conversion.

scholarly journals A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set

2021 ◽  
Vol 22 (1) ◽  
Author(s):  
Mohsen Mojahed ◽  
Amir Sabbagh Molahosseini ◽  
Azadeh Alsadat Emrani Zarandi
Keyword(s):  
Dynamic Range ◽  
High Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
Asymmetric Cryptography ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Sign Detection ◽  
Residue Number ◽  
High Dynamic

The high dynamic range residue number system (RNS) five-moduli { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } has been recently introduced as an arithmetically balanced five-moduli set for computation-intensive applications on wide operands such as asymmetric cryptography algorithms. The previous dedicated design of RNS components for this moduli set is just an unsigned reverse converter. In order to utilize of the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } in applications handling with signed numbers, two important components are needed: Sign Detector and Signed Reverse Converter. However, having both of these components results in high hardware requirements which makes RNS impractical. This paper overcomes to this problem by designing a unified unit which can perform both signed reverse conversion as well as sign detection through the reuse of hardware. To the authors knowledge, this is the first attempt to design sign detector for a moduli set including 2n±3 moduli. In order to achieve a hardware-amenable design, we first improved the performance of the previous unsigned reverse converter for the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 }. Then, we extract a sign detection method from the structure of the reverse converter. Finally, we make the unsigned reverse converter to sign converter through the use of the extracted sign signal from the reverse converter. The experimental results shown that the proposed multifunctional unit has relatively the same performance in terms of area, delay and power-consumption than the previous unsigned reverse converter for the set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } while it can perform two complex signed operations.

scholarly journals Algorithm for Clustering the Moduli of RNS for the Application of Optimization of Time Complexity in Standard Cipher System

2020 ◽  
Vol 9 (7) ◽  
pp. 92-97
Keyword(s):  
High Speed ◽  
High Performance ◽  
Fault Tolerant ◽  
Number System ◽  
Residue Number System ◽  
New Method ◽  
Residue Number ◽  
Residue Numbers ◽  
Performance Computing ◽  
Selection Of

Residue number system (RNS) has emerged as a knocking field of research due to its high speed, fault tolerant, carry free and parallel characteristics. Due to these features it has got important role in high performance computing especially with reduced delay. There are various algorithms have been found as a result of the research with respect to RNS. Additionally, since RNS reduces word length due to the modular operations, its computations are faster compared to binary computations. But the major challenges are the selection of moduli sets for the forward (decimal to residue numbers) and reverse (residue numbers to decimal) conversion. RNS performance is purely depending on how efficiently an algorithm computes / chooses the moduli sets [1]-[6]. This paper proposes new method for selecting the moduli sets and its usage in cryptographic applications based on Schonhage modular factorization. The paper proposes six moduli sets {6qk1, 6qk+1, 6qk+3, 6qk+5, 6qk+7, 6qk+11} for the RNS conversions but the Schonhage moduli sets are expressed as the exponents that creates a large gap between the moduli’s computed. Hence, a new method is proposed to for computing moduli sets that helps in representing all the decomposed values approximately in the same range.

Area Efficient Memoryless Reverse Converter for New Four Moduli Set {2n−1,2n−1,2n+1,22n+1−1}

2018 ◽  
Vol 27 (05) ◽  
pp. 1850075 ◽  
Author(s):  
Ritesh Kumar Jaiswal ◽  
Raj Kumar ◽  
Ram Awadh Mishra
Keyword(s):  
Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
Hardware Complexity ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Mixed Radix Conversion ◽  
Residue Number ◽  
Least Area ◽  
State Of Art

The efficiency of residue number system depends on the reverse converter due to several modulo operations like addition, subtraction and multiplication. In this paper, a design of new four moduli set [Formula: see text], reverse converter is presented. The moduli set have moduli with length ranging from ([Formula: see text]) to ([Formula: see text])-bits. The reverse conversion for moduli set [Formula: see text] has been optimized in existing state of art. Thus, proposed converter is based on two new moduli set [Formula: see text] and utilizes the mixed radix conversion. This converter is memoryless, and occupies least area. The proposed converter is based on carry save adder (CSA) and modulo adder enabling more speed and less hardware complexity for dynamic range of [Formula: see text]-bit, offering good area-delay product.

scholarly journals Improved Perceptual Video Encryption Technique using Residue Number System

2019 ◽  
pp. 111-125
Author(s):  
Salamudeen Alhassan ◽  
Mohammed Muniru Iddrisu ◽  
Mohammed Ibrahim Daabo
Keyword(s):  
Dynamic Range ◽  
Visual Quality ◽  
Number System ◽  
Residue Number System ◽  
Original Video ◽  
Video Encryption ◽  
Reverse Converter ◽  
Residue Number ◽  
Speed Up ◽  
Transmission Speed

In this paper, we propose an enhanced perceptual video encryption technique to speed-up and secure cipher video transmitted across networks using Residue Number System (RNS). The technique proposes a new reverse converter with smaller dynamic range using the moduli set {2n-1, 2n, 2n+1} that is integrated into our previous work of [2]. After encryption, cipher video is encoded into three residual videos that have smaller pixel values and ideal for transmission across networks. Instead of transmitting the three (3) residual videos, the technique effectively transmits and decodes only two (2) of them back into the original video with same visual quality. Experimental results show that the technique enhances transmission speed and security of cipher video across networks.

Perspective and Opportunities of Modulo 2n−1 Multipliers in Residue Number System: A Review

2020 ◽  
Vol 29 (11) ◽  
pp. 2030008
Author(s):  
Raj Kumar ◽  
Ritesh Kumar Jaiswal ◽  
Ram Awadh Mishra
Keyword(s):  
Word Length ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
System A ◽  
Essential Components ◽  
Residue Number ◽  
Speed Up ◽  
Computational Circuits

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.

scholarly journals High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 209181-209190
Author(s):  
Pavel Lyakhov ◽  
Maria Valueva ◽  
Georgii Valuev ◽  
Nikolai Nagornov
Keyword(s):  
High Performance ◽  
Digital Filtering ◽  
Number System ◽  
Residue Number System ◽  
Residue Number

scholarly journals High-Performance RNS Modular Exponentiation by Sum-Residue Reduction

2020 ◽  
Author(s):  
Tao Wu
Keyword(s):  
High Performance ◽  
Computer Arithmetic ◽  
Number System ◽  
Residue Number System ◽  
Modular Exponentiation ◽  
Number Systems ◽  
Diffie Hellman ◽  
Residue Number ◽  
Diffie Hellman Key Exchange ◽  
Rsa Cryptography

Abstract Modular exponentiation is fundamental in computer arithmetic and is widely applied in cryptography such as ElGamal cryptography, Diffie-Hellman key exchange protocol, and RSA cryptography. Implementation of modular exponentiation in residue number system leads to high parallelism in computation, and has been applied in many hardware architectures. While most RNS based architectures utilizes RNS Montgomery algorithm with two residue number systems, the recent modular multiplication algorithm with sum-residues performs modular reduction in only one residue number system with about the same parallelism. In this work, it is shown that high-performance modular exponentiation and RSA cryptography can be implemented in RNS. Both the algorithm and architecture are improved to achieve high performance with extra area overheads, where a 1024-bit modular exponentiation can be completed in 0.567 ms in Xilinx XC6VLX195t-3 platform, costing 26,489 slices, 87,357 LUTs, 363 dedicated multipilers of $18\times 18$ bits, and 65 Block RAMs.

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