Integrated circuits manufacturing still requires several wet etching operations in presence of photo resist. They are usually used to define the gate oxides or metal in a high k metal gate, gate first integration scheme. During this process step, the resist is used for masking and prevents the underneath material from being etched away. Wet treatments are preferred to plasma etching to perform this operation. Indeed, a smooth channels surface is mandatory to obtain a high carriers mobility. It is then critical to avoid any resist lift-off during the wet treatment in order to guarantee the underlying layers integrity. The observation of the lift-off phenomenon (figure 1) points out two possible root causes: 1) a lateral degradation of the covalent bonds at the interface between the polymer and the underlying material, and 2) a vertical resist degradation, due to the penetration of the etching chemicals into the resist down to the underlying material. Previous observations tend to link the lift-off severity to the bake temperature and the oxidation state of the surface on which the resist is coated.
Heteroepitaxial growth of high- k gate oxides on silicon: insights from first-principles calculations on Zr on Si(0 0 1)