Alternate Gate Oxides for Silicon Mosfets Using High-k Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
C. A. Billman ◽  
P. H. Tan ◽  
K. J. Hubbard ◽  
D. G. Schlom
Keyword(s):  
Dielectric Constant ◽  
Thermodynamic Stability ◽  
Thermodynamic Data ◽  
Gate Dielectric ◽  
Inorganic Compounds ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Binary Oxides ◽  
High K ◽  
Ranked List

ABSTRACTHigh K (dielectric constant) and silicon-compatibility are essential for an alternative gate dielectric for use in silicon MOSFETs. Thermodynamic data were used to comprehensively evaluate the thermodynamic stability of binary oxides and binary nitrides in contact with silicon at 1000 K. Using the Clausius-Mossotti equation and ionic polarizabilities, the K of all known inorganic compounds composed of Si-compatible binary oxides was estimated. A ranked list of alternate gate oxide candidates that are likely to possess both high K and silicon-compatibility is given.

scholarly journals Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet
Keyword(s):  
Dielectric Constant ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage ◽  
Mos Devices ◽  
High K ◽  
Carrier Trap ◽  
High Dielectric ◽  
Very High ◽  
Tunnelling Current

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.

Thermodynamic stability of binary oxides in contact with silicon

1996 ◽  
Vol 11 (11) ◽  
pp. 2757-2776 ◽  
Author(s):  
K. J. Hubbard ◽  
D. G. Schlom
Keyword(s):  
Rare Earth ◽  
Dynamic Stability ◽  
Thermodynamic Stability ◽  
Thermodynamic Data ◽  
Alkaline Earth ◽  
Binary Oxide ◽  
Sufficient Data ◽  
Comprehensive Investigation ◽  
Oxide Interfaces ◽  
Binary Oxides

Using tabulated thermodynamic data, a comprehensive investigation of the thermo-dynamic stability of binary oxides in contact with silicon at 1000 K was conducted. Reactions between silicon and each binary oxide at 1000 K, including those involving ternary phases, were considered. Sufficient data exist to conclude that all binary oxides except the following are thermodynamically unstable in contact with silicon at 1000 K: Li2O, most of the alkaline earth oxides (BeO, MgO, CaO, and SrO), the column IIIB oxides (Sc2O3, Y2O3, and Re2O3, where Re is a rare earth), ThO2, UO2, ZrO2, HfO2, and Al2O3. Of these remaining oxides, sufficient data exist to conclude that BeO, MgO, and ZrO2 are thermodynamically stable in contact with silicon at 1000 K. Our results are consistent with reported investigations of silicon/binary oxide interfaces and identify candidate materials for future investigations.

scholarly journals Fabrication and Characterization of amorphous Lanthanum Zirconate Gate Capacitors

2019 ◽  
Vol 8 (11) ◽  
pp. 2868-2872
Keyword(s):  
Thin Film ◽  
Dielectric Constant ◽  
Electrical Properties ◽  
Gate Dielectric ◽  
Semiconductor Device ◽  
Oxide Semiconductor ◽  
Future Application ◽  
High K ◽  
La Doped ◽  
High K Gate Dielectric

A novel high-k gate dielectric material, i.e., Lanthanum-doped Zirconium oxide (La-doped ZrO2 ), has been thoroughly studied for applications in future metal oxide semiconductor field-effect transistor (MOSFET). The film's structural, chemical and electrical properties are investigated experimentally. The incorporation of La into ZrO2 impacted the electrical properties in terms of leakage current while not sacrificing its dielectric constant. The dielectric constant of 25 is achieved which is calculated from the C-V analysis taken from Agilent 1500A Semiconductor Device Analyzer. XRD, FTIR, EDX analysis were conducted to confirm the stoichiometry and bond formation of La2Zr2O7 . The sol-gel spin coating method is adopted to form a uniform thin film over p-Silicon substrate and Aluminium is evaporated in the eBeam technique as gate electrode to form an MIS capacitor. The La-doped ZrO2 film is hence a potential high-k gate dielectric for future application in MIS thin film transistors.

scholarly journals Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

2021 ◽  
Vol 11 (1) ◽  
pp. 240
Author(s):  
Hakkee Jung
Keyword(s):  
Dielectric Constant ◽  
Oxide Film ◽  
Gate Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Subthreshold Swing ◽  
Asymmetric Structure ◽  
Double Gate ◽  
High K

In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

Analysis of ZrxSiyOz as High-k Dielectric for 4H-SiC MOSFETs

2018 ◽  
Vol 924 ◽  
pp. 939-942 ◽  
Author(s):  
Maria Cabello ◽  
Aneesha Varghese ◽  
Josep Montserrat ◽  
José Rebollo ◽  
Jean Manuel Decams ◽  
...  
Keyword(s):  
Thermodynamic Stability ◽  
Gate Dielectric ◽  
Interface Quality ◽  
K Value ◽  
High K ◽  
High K Dielectric ◽  
Process Compatibility

This paper deals with investigation and fabrication of 4H-SiC MOSFETs with a high-k dielectric close to ZrSiO4. We are looking for the optimal stochiometry in order to obtain full benefits of its large bandgap, a k value higher than that of SiO2, thermodynamic stability on SiC, a good interface quality and process compatibility with SiC technology. Several Si/Zr ratios have been tested with the purpose of obtaining the most favorable dielectric configuration. The first test devices have been manufactured successfully with a stack gate dielectric consisting of a thin SiO2interlayer and a ZrxSiyOz(theoretical Si/Z=0.7) layer on top.

4H-SiC MOSFETs Using Thermal Oxidized Ta2Si Films as High-k Gate Dielectric

2005 ◽  
Vol 483-485 ◽  
pp. 713-716 ◽  
Author(s):  
Amador Pérez-Tomás ◽  
Phillippe Godignon ◽  
Narcis Mestres ◽  
Josep Montserrat ◽  
José Millan
Keyword(s):  
Dielectric Constant ◽  
Dielectric Layer ◽  
Room Temperature ◽  
Gate Dielectric ◽  
Gate Insulator ◽  
High K ◽  
Dry Oxidation ◽  
High K Dielectric ◽  
Si Films ◽  
Mis Capacitors

Oxidized Ta2Si layers have been used as high-k dielectric layer for 4H-SiC MOSFETs. The gate insulator was grown by dry oxidation of 40nm deposited Ta2Si during 1h at 1050oC. The dielectric constant obtained from 4H-SiC MIS capacitors is ~20 with an insulator thickness of 150nm. These devices exhibit adequate subthreshold, saturation and drive characteristics. For the MOSFETs fabricated on a p-implanted and annealed region, a peak mobility up to 45cm2/Vs has been extracted. The specific on-resistance of this device is 29mW·cm2 at room temperature with VDS=0.2V and VGS=14V.

Ellipsometry Measurement Accuracy of Gate Oxides under Polysilicon

2003 ◽  
Vol 782 ◽  
Author(s):  
Gary Jiang ◽  
Don Pelcher ◽  
Daewon Kwon ◽  
Jana Clerico ◽  
George Collins
Keyword(s):  
Gate Dielectric ◽  
Optical Feedback ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Visible Spectral Range ◽  
Dielectric Films ◽  
High Yield ◽  
Gate Oxides ◽  
Airborne Contamination ◽  
Accuracy And Repeatability

ABSTRACTPrecisely controlling the thickness of ultrathin silicon dioxide (SiO2) gate dielectric films is critical for high yield advanced generation semiconductor manufacturing. Advanced methods for producing ultrathin gates deposit both the gate dielectric and the polysilicon (poly-Si) gate electrode in a single cluster tool. This avoids the opportunity for adsorption of molecular airborne contamination (MAC) between deposition of the two layers, but necessitates measuring gate oxide thickness through a thick poly-Si layer.Variations in poly-Si grain size, amorphous silicon content, and roughness, make it very difficult to model the optical feedback in the visible spectral range to resolve ultrathin (10–20 Å) gate oxides with sufficient accuracy and repeatability for process control.This paper studies the optical behavior of the poly-Si/dielectric filmstack from 190 nm to 900 nm and the physical properties of the poly-Si layer. A more accurate modeling method is proposed to characterize the poly-Si and its top roughness layer using effective medium approximation (EMA) models. Using the new model, both a spectroscopic ellipsometer (SE) and a multi-angle multi-wavelength laser ellipsometer (MWLE) were employed to measure wafers with different poly-Si and gate oxide thicknesses. TEM was used to characterize the film thickness while roughness was determined using AFM. Good correlation was obtained between the TEM, AFM, and ellipsometry results. Excellent repeatability (0.04 Å 1σ on a 15 Å gate oxide for 10 days) and across the wafer uniformity (0.2 Å 1σ for a 49-point map) were also achieved when measuring gate dielectric films under the poly-Si with the MWLE.

The Properties of Mfmos and MFOS Capacitors with High K Gate Oxides for one Transistor Memory Applications

2000 ◽  
Vol 655 ◽  
Author(s):  
Tingkai Li ◽  
Sheng Teng Hsu ◽  
Hong Ying ◽  
Bruce Ulrich
Keyword(s):  
Thin Films ◽  
Dielectric Constant ◽  
Silicon Substrate ◽  
High Dielectric Constant ◽  
Basic Mechanism ◽  
Germanium Oxide ◽  
Gate Oxides ◽  
High K ◽  
High Dielectric ◽  
Memory Applications

AbstractMFMOS and MFOS (M: Metal, F: Ferroelectrics, O: Oxide, S: Silicon) capacitors with high k gate oxides, such as ZrO2, HfO2 thin films, have been fabricated for one transistor memory applications. Experimental results showed that ZrO2 and HfO2 have no serious reaction or diffusion into silicon substrate. Due to their high dielectric constant, the operation voltages of MFMOS capacitors are reduced. The MFMOS capacitor exhibits 2V memory window. For lead germanium oxide (PGO) on ZrO2 and PGO on HfO2 MFOS memory cells the memory windows are 1.8 V and 1.6 V, respectively, which are large enough for one-transistor memory applications. The basic mechanism for one-transistor memory applications was also discussed.

scholarly journals Performance Assessment of Dual Material Stack Gate Oxide TFET using Dielectric Pocket

2021 ◽  
Author(s):  
Dharmender Kumar ◽  
Kaushal Nigam
Keyword(s):  
Computer Aided Design ◽  
Gate Dielectric ◽  
Gate Oxide ◽  
Subthreshold Swing ◽  
Power Switching ◽  
High K ◽  
Work Functions ◽  
High K Dielectric ◽  
The Impact ◽  
Dual Material

Abstract This paper investigates the impact of lowK and high-K dielectric pockets on DC characteristics, analog/RF, and linearity performance of dual material stack gate oxide-tunnel field-effect transistor (DMSGODP-TFET). For this, a stack gate oxide with workfunction is considered to enhance the ON-state current (ION ), lower ambipolar current (Iamb) and lower the subthreshold swing. For this case, the gate electrode is tri-segmented, named as tunnel gate (M1), control gate (M2) and auxiliary gate (M3) with different gate lengths (L1, L2, L3) and work functions (φ1, φ2, φ3), respectively. To maintain dual-work functionality, the possible combinations of these work functions are considered. Technology computer-aided design (TCAD) simulations are performed and noted that the workfunction combination (φ1 = φ3 < φ2) outperforms as compared to other combinations. Where φ1 on the source side is used to enhance the ION , while φ3 (equal to φ1) is used on the drain side to minimize the Iamb. To further enhance the device performance, a high-K dielectric pocket is considered at the drain junction to suppress the Iamb whereas, a low-K dielectric pocket is employed at the source junction to enhance the ION . Moreover, length of gate segments, dielectric pocket height, and thickness are optimized to achieve a better switching ratio, subthreshold swing (SS) and reduce the Iamb which helps in the gain of device and design of analog/RF circuits. The proposed device as compared to dual material control gate-dielectric pocket-TFET (DMCG-DP-TFET) with SiO2 gate oxide shows improvement in ION /IOF F (∼ 4.23 times), 84 % increase in transconductance (gm), 136 % increase in cut-off frequency (fT ), 126 % increase in gain bandwidth product (GBP), point subthreshold swing (15.8 mV/decade) and other significant improvements in linearity figure of merits (FOMs) making the proposed device useful for low power switching, analog/RF and linearity applications.

scholarly journals Ambipolar Current Suppression, Analog/RF and Linearity Performance Improvement of Dual Material Stacked Gate Oxide TFET with Dielectric Pocket

2021 ◽  
Author(s):  
dharmender nishad ◽  
kaushal Nigam
Keyword(s):  
Gate Dielectric ◽  
Rf Circuits ◽  
Gate Oxide ◽  
High K ◽  
Ambipolar Current ◽  
High K Dielectric ◽  
Rf Performance ◽  
The Impact ◽  
Dual Material ◽  
Low K

Abstract In this article, the impact of high-K and low-K dielectric pockets on DC, analog/RF, and linearity performance parameters of dual material stacked gate oxide-dielectric pocket-tunnel field-effect transistor (DMSGO-DP-TFET) is investigated. In this regard, a stacked gate oxide (SiO2 + HfO2) with workfunction engineering is taken into consideration to improve the ON-state current (ION ), and suppress the ambipolar current (Iamb). To further improve the performance of the device, a high-K dielectric pocket (HfO2) is used at the drain-channel interface to suppress the Iamb, and at the source-channel interface a low-K dielectric pocket is used to improve the ION and analog/RF performance. Moreover, length of stacked gate segments (L1, L2, L3), pocket height, and thickness are optimized to attain better ION /IOFF ratio, and suppress the Iamb which helps to achieve higher gain and design of analog/RF circuits. The DMSGO-DP-TFET outperforms the dual material control gate-dielectric pocket-TFET (DMCG-DP-TFET) with SiO2 gate oxide and shows increment in ION /IOFF (∼ 4.23 times), 84 % increment in transconductance (gm), 136 % increment in cut-off frequency (fT ), 126 % increment in gain-bandwidth-product (GBP), and better linearity performance parametrs such as gm2 ,gm3, VIP2, VIP3 and IIP3 making the proposed device useful for low power and radio frequency applications.

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