The dominant portion of power dissipation in
CMOS adder circuits, due to logic transitions, varies as the
square of the supply, significant savings in power
dissipation may be exacted by operating with reduced
supply voltage. If the supply voltage is reduced while
threshold voltage stays same, the noise margins will
reduce. Addition is a crucial process because it usually
involve carry ripple steps which must propagate a carry
signal from each bit to it’s higher bit position. This results
in a substantial circuit delay. The adder which lies in the
crucial delay path will effectively determine the system
overall speed. To improve noise margins, the threshold
voltages must also be made smaller. However subthreshold leakage current increases exponentially when
threshold voltage is reduced. The higher static dissipation
may then offset the reduction in transitions portion of the
dissipation. Hence the devices needed to have threshold
voltages that maximizes the net reduction in the
dissipation. Addition is an obligatory operation that is
crucial to processing the fundamental arithmetic
operations. Due to the potential versatility of adders in this
contemporary research field, the existing adders and
adder designs currently intended for future low voltage
and low power environments. This can be achieved by the
CMOS adders namely Parallel Adder, Ripple Carry
Adder(RCA), Carry Look Ahead Adder(CLA), Carry
Select Adder(CSL), Carry Save Adder(CSA), Carry Skip
Adder(CSK), Conditional Sum Adder(COS).
Design of a Low-Power Carry Look-Ahead Adder Using Multi-Threshold Voltage CMOS