scholarly journals Modified Ion Implantation Based New Subthreshold Device Design & Threshold Voltage Modelling for Ultra Low Power Applications

2018 ◽  
Vol 2 (1) ◽  
Author(s):  
Hossain Munem ◽  
Chowdhury Masud H
Keyword(s):  
Ion Implantation ◽  
Low Power ◽  
Threshold Voltage ◽  
Device Design ◽  
Ultra Low Power

An Ultra Low-Voltage Ultra Low-Power CMOS Threshold Voltage Reference

2007 ◽  
Vol E90-C (10) ◽  
pp. 2044-2050 ◽  
Author(s):  
L. H.C. FERREIRA ◽  
T. C. PIMENTA ◽  
R. L. MORENO
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Low Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Low Power Cmos

scholarly journals Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications

2015 ◽  
Vol 12 (3) ◽  
pp. 20141122-20141122 ◽  
Author(s):  
Xin-Xiang Lian ◽  
I-Chyn Wey ◽  
Chien-Chang Peng ◽  
Zhi-Qun Cheng
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Ultra Low Power ◽  
Near Threshold

scholarly journals High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

2021 ◽  
Author(s):  
Prashant Kumar ◽  
Munish Vashishath ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Analytical Model ◽  
Threshold Voltage ◽  
Figure Of Merit ◽  
Double Gate ◽  
Short Channel ◽  
Ultra Low Power ◽  
High K ◽  
Channel Effects ◽  
High K Dielectric

Abstract This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29% improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

scholarly journals Stability analysis of Sub-threshold 6T SRAM cell at 45 nm for IoT application

2019 ◽  
Vol 8 (2) ◽  
pp. 2434-2438
Keyword(s):  
Stability Analysis ◽  
Low Power ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Stability Parameter ◽  
Threshold Region ◽  
Ultra Low Power ◽  
Noise Margin ◽  
Sram Cell ◽  
Power Application

In ultra-Low power application the supply volt- age in the circuit is as minimum as possible to correct perform the operation. Reducing the supply voltage below the threshold Voltage of transistor is known as sub threshold voltage that affects the delay as well as stability parameter of the Circuit. In this paper body biased technique is applied at standard 6T SRAM which improve the static Current Noise Margin(SINM) and Write trip Current by the factor of 4.15 times and 4.7 times respectively from the Conventional (conv) 6T SRAM. SINM defined the read stability whereas WTI are write ability Parameters of the circuit. In the Sub threshold region delay parameter of the circuit increased, but in this paper delay and power of the proposed circuit are going to be degrades 2.34 times and 4.39 times from the conv. 6T SRAM at different Process Corner i.e. the Performance of the device get increased. In this paper conventional (Conv.)6T and Proposed(PP) 6T both have same W/L ratio at supply voltage of 400mv

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