scholarly journals Adaptive Biasing Low Power Amplifier Using CMOS Technology

2015 ◽  
Vol 15 (10) ◽  
pp. 1256-1260
Author(s):  
Hamid Abolfazli Ghamsari ◽  
Mahdi Pirmoradia
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Cmos Technology ◽  
Adaptive Biasing

scholarly journals Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
Muhammad Ovais Akhter ◽  
Najam Muhammad Amin
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Cmos Technology ◽  
High Gain ◽  
The Novel ◽  
Ultra Low Power ◽  
Design And Optimization ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier ◽  
Insertion Losses

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

scholarly journals LOW POWER SI-BASED POWER AMPLIFIER FOR HEALTHCARE APPLICATION

2016 ◽  
Vol 8 (9) ◽  
pp. 307 ◽  
Author(s):  
Wei Cai ◽  
Cheng Li ◽  
Heng Gu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Amplifier ◽  
Process Variations ◽  
Cmos Technology ◽  
Total Power ◽  
Power Added Efficiency ◽  
Trade Offs ◽  
Total Power Consumption ◽  
Class B

<p><strong>Objective: </strong>The objective of this research was to design a 2.4 GHz class B Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design.</p><p><strong>Methods: </strong>This paper introduces the design of a 2.4GHz class B power amplifier designed as dual gate topology. This class B power amplifier could transmit 26dBm output power to a 50Ω load. The power added efficiency was 60% minimum and the power gain was 90dB, the total power consumption was 6.9 mW.</p><p><strong>Results:</strong> Besides, accurate device modeling, is needed, due to the leakage and process variations.</p><p><strong>Conclusion</strong>:<strong> </strong>The performance of the power amplifier meets the specification requirements of the desired.</p>

scholarly journals Efficiency Analysis of Low Power Class-E Power Amplifier

2014 ◽  
Vol 8 (5) ◽  
pp. 19
Author(s):  
Mousa Yousefi ◽  
Ziaadin Daie Koozehkanani ◽  
Jafar Sobhi ◽  
Hamid Jangi ◽  
Nasser Nasirezadeh
Keyword(s):  
Low Power ◽  
Output Power ◽  
Power Amplifier ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Efficiency Analysis ◽  
Simulation Results ◽  
On Chip ◽  
Power Class ◽  
Class E

This paper presents an analysis of effect of inductor and switch losses on output power and efficiency of low power class-E power amplifier. This structure is suitable for integrated circuit implementation. Since on chip inductors have large losses than the other elements, the effect of their losses on efficiency has been investigated. Equations for the efficiency have been derived and plotted versus the value of inductors and switch losses. Derived equations are evaluated using MATLAB. Also, Cadence Spectre has been used for schematic simulation. Results show a fair matching between simulated power loss and efficiency and MATLAB evaluations. Considering the analysis, the proposed power amplifier shows about 13 % improvement in power effiency at 400 MHz and -2 dBm output power. It is simulated in 0.18 ?m CMOS technology.

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