scholarly journals Design and Implementation of Vehicle Pedestrian Detection System Based on FPGA

2011 ◽  
Vol 2-3 ◽  
pp. 495-500
Author(s):  
Xue Wen Ma ◽  
Shuang Ma ◽  
Meng Yao Li ◽  
Mei Ling Jin

The vehicle pedestrian detection system is a kind of solution to car driver assistance. The system can detect pedestrian in dangerous and send early warning to drivers automatically. Therefore, it has practical significance to develop a robust、real-time and stability pedestrian detection system which can reduce and avoid pedestrian accidents effectively. This article completes the vehicle pedestrian detection system based on FPGA. It used the cyclone II EP2C70 DSP development board provided by the Altera Corporation. By testing, the system can determine a size of 320 × 240 grayscale image takes about 723ms at the clock frequency in the 100MHZ. It achieves the desired functionality. The system has better real-time and reliability. At the same time, it has small size, easy to control and the most important is that it has broad application prospects.

Sensors ◽  
2018 ◽  
Vol 18 (4) ◽  
pp. 1174 ◽  
Author(s):  
Jian Luo ◽  
Chang Lin

In this study, we propose a real-time pedestrian detection system using a FPGA with a digital image sensor. Comparing with some prior works, the proposed implementation realizes both the histogram of oriented gradients (HOG) and the trained support vector machine (SVM) classification on a FPGA. Moreover, the implementation does not use any external memory or processors to assist the implementation. Although the implementation implements both the HOG algorithm and the SVM classification in hardware without using any external memory modules and processors, the proposed implementation’s resource utilization of the FPGA is lower than most of the prior art. The main reasons resulting in the lower resource usage are: (1) simplification in the Getting Bin sub-module; (2) distributed writing and two shift registers in the Cell Histogram Generation sub-module; (3) reuse of each sum of the cell histogram in the Block Histogram Normalization sub-module; and (4) regarding a window of the SVM classification as 105 blocks of the SVM classification. Moreover, compared to Dalal and Triggs’s pure software HOG implementation, the proposed implementation‘s average detection rate is just about 4.05% less, but can achieve a much higher frame rate.


Author(s):  
G. Belgiovine ◽  
M. Capecci ◽  
L. Ciabattoni ◽  
M. C. Fiorentino ◽  
G. Foresi ◽  
...  

2020 ◽  
Vol 48 (9) ◽  
pp. 3203-3210
Author(s):  
Guan Xiao Cun ◽  
Shuai Wang ◽  
Denghua Guo ◽  
Shaohua Guan ◽  
Baolong Liu ◽  
...  

2013 ◽  
Vol 765-767 ◽  
pp. 1546-1549
Author(s):  
Xu Ping Wang ◽  
Xiao Hu Chen ◽  
Chun Jiang Yao ◽  
Yao Ding ◽  
Shu Xiang Gao

According to the current status of maintenance training, a framework of desktop virtual maintenance training platform was proposed on the basis of the NGRAIN ,making full use of advanced CAD technology and virtual reality technology. At last take the dump trucks as example, which proved that equipment virtual maintenance training can largely improve the cost-effectiveness of the maintenance training. The platform is a portable, economical solution for maintenance training, which not only can meet the needs of the training mission, but also provide a reference for the other virtual maintenance training system. In the future, the platform will have a very important practical significance and broad application prospects.


2013 ◽  
Vol 333-335 ◽  
pp. 1060-1064 ◽  
Author(s):  
Yang Lu ◽  
Chao Gao

This work presents the design and implementation of drivers fatigue detection system based on FPGA to prevent car accidents. According to the bright pupil phenomenon, which is produced by the retina when the incident lights wavelength is 850 nm, drivers eyes can be detected easily. While acquiring the real-time video of the drivers face by camera, the system accomplishes the detection of drivers eyes by using a simplified PCNN (pulse coupled neural network) and the computation of the PERCLOS (Percentage of Eye Closure) to decide whether the driver is fatigue or not. All the designing and accomplishments of the system are based on the FPGA platform Xilinx Virtex Pro Development Board. During the experiments, the system has the ability of processing 25 frames/sec, which is the speed of collection of the used camera. Also, the fatigue detection system has good stability and accuracy.


2013 ◽  
Vol 14 (3) ◽  
pp. 1346-1359 ◽  
Author(s):  
Antonio Prioletti ◽  
Andreas Mogelmose ◽  
Paolo Grisleri ◽  
Mohan Manubhai Trivedi ◽  
Alberto Broggi ◽  
...  

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