The Research of the Power Supply System of Embedded Portable Devices

2011 ◽  
Vol 127 ◽  
pp. 496-500
Author(s):  
Wei Cheng
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Power Supply System ◽  
Functional Integration ◽  
Portable Devices ◽  
Dynamic Power Management ◽  
Portable Equipment ◽  
Work Time ◽  
Management Technology ◽  
System Power

Portable devices are mostly powered by battery. With the products tending to the direction of light, thin, short and multi-functional integration, the power requirements of portable devices are increasing all the time, but the energy density of battery is far behind the speed, the improvement of performance relies heavily on the power management technology. Therefore, it’s needed that manage the power of whole system with the integrated viewpoint to reduce power consumption and extend the system work time. After the analysis and research for power management technologies, one kind of a combination of hardware and software power management solution is proposed. The power management IC with embedded Linux operating system's Dynamic Power Management technology, better to reduce system power consumption, meets the requirements of the power system supplied by portable equipment.

INTELLIGENT POWER MANAGEMENT FOR EMBEDDED WI-FI DEVICES

2012 ◽  
Vol 21 (01) ◽  
pp. 1250003 ◽  
Author(s):  
WEIYIN HONG ◽  
XIN KUANG ◽  
JIANHUA SHEN ◽  
TONGQUAN WEI
Keyword(s):  
Power Management ◽  
Energy Savings ◽  
Low Power Design ◽  
System Level ◽  
Dynamic Power Management ◽  
Research Attention ◽  
And Performance ◽  
Application Requirements ◽  
Intelligent Power Management ◽  
System Power

With the increasing deployment of Wi-Fi devices in portable embedded systems, the low power design at system level has attracted considerable research attention in the recent past. In this paper, based on hardware features and software architecture of the embedded Wi-Fi devices, we focus on dynamic power management, dynamic frequency scaling, and their influences upon the system power and performance. We propose effective and realizable system power management solution and application modes under various application requirements, such as response, bandwidth, and speed. Experimental results show that the proposed solutions can achieve significant energy savings.

scholarly journals An Adaptive and Integrated Low-Power Framework for Multicore Mobile Computing

2017 ◽  
Vol 2017 ◽  
pp. 1-11 ◽  
Author(s):  
Jongmoo Choi ◽  
Bumjong Jung ◽  
Yongjae Choi ◽  
Seiil Son
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Mobile Computing ◽  
Power Management ◽  
Hot Spot ◽  
Energy Resource ◽  
Mobile Systems ◽  
Dynamic Power Management ◽  
Online Resource ◽  
Dynamic Voltage

Employing multicore in mobile computing such as smartphone and IoT (Internet of Things) device is a double-edged sword. It provides ample computing capabilities required in recent intelligent mobile services including voice recognition, image processing, big data analysis, and deep learning. However, it requires a great deal of power consumption, which causes creating a thermal hot spot and putting pressure on the energy resource in a mobile device. In this paper, we propose a novel framework that integrates two well-known low-power techniques, DPM (Dynamic Power Management) and DVFS (Dynamic Voltage and Frequency Scaling) for energy efficiency in multicore mobile systems. The key feature of the proposed framework is adaptability. By monitoring the online resource usage such as CPU utilization and power consumption, the framework can orchestrate diverse DPM and DVFS policies according to workload characteristics. Real implementation based experiments using three mobile devices have shown that it can reduce the power consumption ranging from 22% to 79%, while affecting negligibly the performance of workloads.

Using DRAM as Cache for Non-Volatile Main Memory Swapping

2016 ◽  
Vol 4 (1) ◽  
pp. 61-71
Author(s):  
Hirotaka Kawata ◽  
Gaku Nakagawa ◽  
Shuichi Oikawa
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Mobile Devices ◽  
Memory Management ◽  
High Performance ◽  
Reducing Power ◽  
Memory Systems ◽  
Main Memory ◽  
Dynamic Power Management ◽  
Memory Space

The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory (NVM), which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the price and capacity of NVM are problematic. Therefore, the authors provide a large memory space without performance degradation by combining NVM with other memory devices. In this study, they propose a design for non-volatile main memory systems that use DRAM as a swap space. This enables both high performance and energy efficient memory management through dynamic power management in NVM and DRAM.

scholarly journals Dynamic Power Management Model for a Wireless Sensor Node

2021 ◽  
Vol 20 ◽  
pp. 57-67
Author(s):  
Rakhee Kallimani ◽  
Sridhar Iyer
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Sensor Node ◽  
Performance Metrics ◽  
Wireless Sensor ◽  
Single Server ◽  
Dynamic Power Management ◽  
Wireless Sensor Node ◽  
Dynamic Power ◽  
The Impact

Dynamic power management (DPM) is an efficient technique to design low-power and energy-efficient nodes for wireless sensor networks. This article demonstrates the stochastic behaviour of an input event arrival which is modelled with first-in first-out (FIFO) queue and a single server. An event-driven sensor node is developed based on semi-Markov model. The article investigates the factors affecting the performance of the individual sensor node with detailed analysis considering power consumption and lifetime to be the performance metrics under study. The results demonstrate the impact of the change in event arrival and the probability of change detection on the performance of the node. It is observed that (i) the number of generated events increases with the change in the average value of the distribution which affects the service time in turn resulting in a variation of the server utilization, and that (ii) the increase in the detection probability increases the power consumption decreasing the lifetime of the node.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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