scholarly journals An Adaptive and Integrated Low-Power Framework for Multicore Mobile Computing

2017 ◽  
Vol 2017 ◽  
pp. 1-11 ◽  
Author(s):  
Jongmoo Choi ◽  
Bumjong Jung ◽  
Yongjae Choi ◽  
Seiil Son
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Mobile Computing ◽  
Power Management ◽  
Hot Spot ◽  
Energy Resource ◽  
Mobile Systems ◽  
Dynamic Power Management ◽  
Online Resource ◽  
Dynamic Voltage

Employing multicore in mobile computing such as smartphone and IoT (Internet of Things) device is a double-edged sword. It provides ample computing capabilities required in recent intelligent mobile services including voice recognition, image processing, big data analysis, and deep learning. However, it requires a great deal of power consumption, which causes creating a thermal hot spot and putting pressure on the energy resource in a mobile device. In this paper, we propose a novel framework that integrates two well-known low-power techniques, DPM (Dynamic Power Management) and DVFS (Dynamic Voltage and Frequency Scaling) for energy efficiency in multicore mobile systems. The key feature of the proposed framework is adaptability. By monitoring the online resource usage such as CPU utilization and power consumption, the framework can orchestrate diverse DPM and DVFS policies according to workload characteristics. Real implementation based experiments using three mobile devices have shown that it can reduce the power consumption ranging from 22% to 79%, while affecting negligibly the performance of workloads.

scholarly journals Dynamic Voltage Scaling With Reduced Frequency Switching And Preemptions

2012 ◽  
pp. 10-14
Author(s):  
Arya Lekshmi Mohan ◽  
Anju S. Pillai
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Voltage Scaling ◽  
Dynamic Voltage Scaling ◽  
Discrete Frequency ◽  
Cpu Time ◽  
Innovative Technique ◽  
Reduced Frequency ◽  
Dynamic Voltage

Dynamic Voltage Scaling is an innovative technique for reducing the power consumption of a processor by utilizing its hardware functionality. Dynamic Voltage Scaling processors are mainly focusing on power management. Such processors can be switch between discrete frequency and voltage levels. The main challenges of Dynamic Voltage Scaling are increased number of preemptions and frequency switching. A part of dynamic energy as well as CPU time is lost due to these processes. To limit such processes, an algorithm is proposed which reduces both unwanted frequency switching and preemptions.

Green Semicondoctor Design Techniques and Challanges

2011 ◽  
pp. 404-411
Author(s):  
Somesh Rajain ◽  
Chetan Shingala ◽  
Ekata Mehul
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Human Life ◽  
Semiconductor Industry ◽  
Low Power Design ◽  
Clock Gating ◽  
Consumer Device ◽  
Carbon Dioxide Co2 ◽  
Design Techniques

The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.

Using DRAM as Cache for Non-Volatile Main Memory Swapping

2016 ◽  
Vol 4 (1) ◽  
pp. 61-71
Author(s):  
Hirotaka Kawata ◽  
Gaku Nakagawa ◽  
Shuichi Oikawa
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Mobile Devices ◽  
Memory Management ◽  
High Performance ◽  
Reducing Power ◽  
Memory Systems ◽  
Main Memory ◽  
Dynamic Power Management ◽  
Memory Space

The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory (NVM), which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the price and capacity of NVM are problematic. Therefore, the authors provide a large memory space without performance degradation by combining NVM with other memory devices. In this study, they propose a design for non-volatile main memory systems that use DRAM as a swap space. This enables both high performance and energy efficient memory management through dynamic power management in NVM and DRAM.

Green Semicondoctor Design Techniques and Challanges

2011 ◽  
pp. 342-350
Author(s):  
Somesh Rajain ◽  
Chetan Shingala ◽  
Ekata Mehul
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Human Life ◽  
Semiconductor Industry ◽  
Low Power Design ◽  
Clock Gating ◽  
Consumer Device ◽  
Carbon Dioxide Co2 ◽  
Design Techniques

The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.

New combined method for low energy consumption in Wireless Sensor Network applications

SIMULATION ◽  
2018 ◽  
Vol 94 (10) ◽  
pp. 873-885 ◽  
Author(s):  
Rym Chéour ◽  
Mohamed Wassim Jmal ◽  
Mohamed Abid
Keyword(s):  
Energy Consumption ◽  
Power Management ◽  
Multiprocessor Scheduling ◽  
Efficient Solutions ◽  
Optimization Techniques ◽  
Wireless Sensor ◽  
Simulation Tool ◽  
Dynamic Power Management ◽  
Energy Management Systems ◽  
Dynamic Voltage

Over the past few years the applications for Wireless Sensor Networks (WSNs) have grown at an ever-increasing rate. However, the evolution of those networks has been reduced by the energy scarcity. It retards the development of the WSN performances required while exploring new applications and improving the WSN potential. Besides, in order to design energy-efficient solutions, it is important to take into account the power dissipation due to noncompliance with time constraints. As a result, we will provide a model of power management that will be simulated and validated by the STORM Simulator (Simulation TOol for Real time Multiprocessor scheduling). However, unlike traditional WSN energy management systems, our power manager reduces the energy consumption through a dual approach: a global and dynamic approach using the analysis of the behavior of the network and a local one applied at the node level. We have relied on energy optimization techniques to yield extensive lifetime for every node battery and mainly both Dynamic Power Management and Dynamic Voltage and Frequency Scaling, which are appropriate for the WSN. This model will be based on a global Earliest Deadline First scheduling policy. Besides, we aim to extend the STORM simulation tool to include those power management techniques.

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