Implementation of DES Encryption Algorithm Based on FPGA and Performance Analysis

2011 ◽  
Vol 130-134 ◽  
pp. 2953-2956
Author(s):  
Ji Hong Lian ◽  
Kai Chen
Keyword(s):  
Performance Analysis ◽  
Processing Speed ◽  
Hardware Description Language ◽  
Encryption Algorithm ◽  
Pipeline Architecture ◽  
Description Language ◽  
Round Function ◽  
Quartus Ii ◽  
Hardware Description ◽  
And Performance

This paper introduced the principle of DES encryption algorithm, designed and realized the DES encryption algorithm with verilog hardware description language, realized module simulation with Quartus II. Two comprehensive considerations from the resources and performance, one pipeline stage control is set in round function to improve the processing speed, Synchronous pipeline architecture of data XOR key round function and Key transformation function is realized on hardware to reducing logic complexity of the adjacent pipeline, round function multiplexing is realized by setting the round counter and controlling the data selector.

Design of a Fast JND Algorithm Based on Discrete Wavelet Transform and its VLSI Implementation

2013 ◽  
Vol 380-384 ◽  
pp. 1538-1541
Author(s):  
Sheng Hui Liu ◽  
Hai Huang ◽  
Zhi Wei Liu ◽  
Su Zhuang
Keyword(s):  
Wavelet Transform ◽  
Integrated Circuits ◽  
Discrete Wavelet Transform ◽  
Hardware Description Language ◽  
Discrete Wavelet ◽  
Pipeline Architecture ◽  
Description Language ◽  
Time Saving ◽  
Full Band ◽  
Hardware Description

The computation of JND is very complex, which makes it difficult to embed it into integrated circuits. To solve this problem, Haar-DWT based JND model is exploited and its corresponding pipeline architecture is developed in this paper. To evaluate its performance, the architecture is modeled with hardware description language, and implemented by SMIC 0.18um technology. The area of JND core is 42052 gates, which is significantly smaller than the full band JND based architecture. From the experiment results, the system goes on well at 161 MHz and achieves 78% time saving compared with the full band JND based architecture.

IP Core Design of 8253 Based on Quartus II

2013 ◽  
Vol 380-384 ◽  
pp. 2941-2944
Author(s):  
Hai Yan Zhang
Keyword(s):  
Software Development ◽  
Hardware Description Language ◽  
Logic Design ◽  
Ip Core ◽  
Description Language ◽  
Development Platform ◽  
Quartus Ii ◽  
Hardware Description ◽  
Gate Array

Provided by ALTERA FPGA/CPLD Quartus II development software development platform. programmable timer/counter 8253s functions and internal circuitry as the basis, combined with programmable gate array (FPGA) products FLEX10KE characteristics, using VHDL hardware description language and schematic Figure two ways 8253 for hierarchical, modular, parameterized logic design. The completed design will be configured to the chip of FLEX10KE,and Proved to be correct.

The Design of Digital Filter Based on DSP Builder

2014 ◽  
Vol 602-605 ◽  
pp. 2641-2644
Author(s):  
Xiao Li Hu ◽  
Li Ding ◽  
Zhi Gang Zhang
Keyword(s):  
Digital Filter ◽  
Hardware Description Language ◽  
Description Language ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Paper Model ◽  
Dsp Builder ◽  
Quartus Ii ◽  
Low Pass ◽  
Hardware Description

This paper model digital FIR low-pass by using the Toolbox of the DSP Builder in MATLAB and convert to VHDL hardware description language, compile and simulation through QUARTUS II software automatically, download and verified by EPF10K20RC208-4.The design combine MATLAB software with FPGA hardware organic ally and completes the transplant of the FIR low-pass filter.

scholarly journals Study of Data Security Algorithms using Verilog HDL

2015 ◽  
Vol 5 (5) ◽  
pp. 1092
Author(s):  
M. Sumathi ◽  
D. Nirmala ◽  
R. Immanuel Rajkumar
Keyword(s):  
Performance Evaluation ◽  
Data Security ◽  
Hardware Description Language ◽  
Performance Study ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Encryption And Decryption ◽  
Different Types ◽  
Hardware Description

This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim.

The Design and Implementation of a Parallel Configurable Paseudorandom Sequence Generator

2012 ◽  
Vol 468-471 ◽  
pp. 1903-1906
Author(s):  
Jun Yang ◽  
Ga Zhao ◽  
Xiao Jun Wang ◽  
Ping Ping Shu ◽  
Heng Fen Yang
Keyword(s):  
Model Simulation ◽  
Hardware Description Language ◽  
Linear Feedback ◽  
Random Series ◽  
Description Language ◽  
M Sequence ◽  
Quartus Ii ◽  
Hardware Description ◽  
Feedback Shift Register ◽  
Sequence Generator

In this paper, we study the implements a data rate can be adjusted, m series can be equipped with pseudo-random series of sequence generator. This design in the basis of linear feedback shift register, through the linear feedback function to produce mould the longest m sequence. In order to carry on it, we use the hardware description language VHDL, take advantage of the FPGA reconfigurability and flexibility, using Quartus II 8.0 for the integrated wiring, and give the Model simulation waveforms. For the sake of verifying the feasibility of this design, we adapt it to the DE2 board, and with an oscilloscope and other equipment were tested.

Design and Simulation on High Speed FFT Processor in Radar Signal Processing

2012 ◽  
Vol 461 ◽  
pp. 333-337 ◽  
Author(s):  
Shun Xin Li ◽  
Yu Fan Mo
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Hardware Description Language ◽  
Radar Signal ◽  
Radar Signal Processing ◽  
Simulation Tool ◽  
Description Language ◽  
Fft Processor ◽  
Quartus Ii ◽  
Hardware Description

Based on the high-speed, real-time and high precision of radar signal processing, FFT arithmetic is utilized in the radar signal processing and FFT processor is designed and implemented. The proposed processor adopts radix-2 FFT algorithm. FFT computing based on FPGA has the advantages of high speed, less resource occupancy, easy algorithm and convenient system debugging and implementation. It is composed employing VHDL as hardware description language, FPGA as the logic controller, Quartus II as designing and synthesis simulation tool. The simulation results indicated FFT processor approached the request of the radar signal processing and it is suitable for the application of high-speed signal processing

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