Design and Simulation on High Speed FFT Processor in Radar Signal Processing

2012 ◽  
Vol 461 ◽  
pp. 333-337 ◽  
Author(s):  
Shun Xin Li ◽  
Yu Fan Mo
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Hardware Description Language ◽  
Radar Signal ◽  
Radar Signal Processing ◽  
Simulation Tool ◽  
Description Language ◽  
Fft Processor ◽  
Quartus Ii ◽  
Hardware Description

Based on the high-speed, real-time and high precision of radar signal processing, FFT arithmetic is utilized in the radar signal processing and FFT processor is designed and implemented. The proposed processor adopts radix-2 FFT algorithm. FFT computing based on FPGA has the advantages of high speed, less resource occupancy, easy algorithm and convenient system debugging and implementation. It is composed employing VHDL as hardware description language, FPGA as the logic controller, Quartus II as designing and synthesis simulation tool. The simulation results indicated FFT processor approached the request of the radar signal processing and it is suitable for the application of high-speed signal processing

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

scholarly journals FPGA Implementation of an Efficient FFT Processor for FMCW Radar Signal Processing

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6443
Author(s):  
Jinmoo Heo ◽  
Yongchul Jung ◽  
Seongjoo Lee ◽  
Yunho Jung
Keyword(s):  
Signal Processing ◽  
Detection Rate ◽  
Continuous Wave ◽  
Vital Signs ◽  
Radar Signal ◽  
Radar Signal Processing ◽  
Fmcw Radar ◽  
Design And Implementation ◽  
Fft Processor ◽  
Point Operator

This paper presents the design and implementation results of an efficient fast Fourier transform (FFT) processor for frequency-modulated continuous wave (FMCW) radar signal processing. The proposed FFT processor is designed with a memory-based FFT architecture and supports variable lengths from 64 to 4096. Moreover, it is designed with a floating-point operator to prevent the performance degradation of fixed-point operators. FMCW radar signal processing requires windowing operations to increase the target detection rate by reducing clutter side lobes, magnitude calculation operations based on the FFT results to detect the target, and accumulation operations to improve the detection performance of the target. In addition, in some applications such as the measurement of vital signs, the phase of the FFT result has to be calculated. In general, only the FFT is implemented in the hardware, and the other FMCW radar signal processing is performed in the software. The proposed FFT processor implements not only the FFT, but also windowing, accumulation, and magnitude/phase calculations in the hardware. Therefore, compared with a processor implementing only the FFT, the proposed FFT processor uses 1.69 times the hardware resources but achieves an execution time 7.32 times shorter.

scholarly journals Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chenn-Jung Huang ◽  
I-Yen Chang
Keyword(s):  
High Speed ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Throughput Rate ◽  
Cell Library ◽  
Conversion Algorithm ◽  
Hardware Description ◽  
Simulation Results

A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.

scholarly journals Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Oscar Montiel-Ross ◽  
Jorge Quiñones ◽  
Roberto Sepúlveda
Keyword(s):  
Parallel Programming ◽  
High Speed ◽  
High Performance ◽  
Hardware Description Language ◽  
System Response ◽  
Description Language ◽  
Tuning Method ◽  
Hardware Description ◽  
Ip Cores ◽  
Fuzzy Pd

This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

scholarly journals Space Vector Pulse Width Modulation for High-Speed Induction Motor Implemented in Nios II Softcore Processor

2018 ◽  
Vol 3 (1) ◽  
pp. 99-107
Author(s):  
Maciej Chojowski
Keyword(s):  
Induction Motor ◽  
Pulse Width ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Classical Method ◽  
Hardware Description Language ◽  
Description Language ◽  
Space Vector ◽  
Nios Ii ◽  
Hardware Description

Abstract The purpose of the article was to present the idea of space vector pulse width modulation (SVPWM) and implementation in Nios II softcore processor. The SVPWM module was described in a classical method in hardware description language both as an independent structure and as an additional component to softcore processor. The available methods were compared, and the experiment was carried out in the laboratory to test implemented SVPWM algorithm using high-speed induction motor.

scholarly journals PERANCANGAN DAN IMPLEMENTASI ARSITEKTUR DEMAPPER 64-QAM DI FPGA

2017 ◽  
Author(s):  
Achmad Rizal Mauludin ◽  
Rina Pudji Astuti ◽  
Denny Darlis
Keyword(s):  
High Speed ◽  
Short Message Service ◽  
Hardware Description Language ◽  
Short Message ◽  
Least Significant Bit ◽  
Description Language ◽  
Error Process ◽  
Message Service ◽  
Hardware Description ◽  
Gate Array

Sistem telekomunikasi bertujuan untuk mengirimkan sinyal dari sumber informasi yang dapatberbentuk suara, pesan singkat atau Short Message Service (SMS), gambar, video dan layanan data ke tujuanyang diinginkan. Informasi yang akan dikirimkan akan diubah menjadi sinyal yang dapat dilewati mediatransmisi, dan agar sinyal yang diterima disisi penerima dapat dibaca, diperlukan demodulator yang dapatmengubah sinyal yang diterima menjadi informasi seperti yang dikirimkan. Demodulator 64-QuadratureAmplitude Modulation (QAM) adalah salah satu jenis demodulator yang mampu mendemodulasi sinyalfrekuensi tinggi.Dalam tugas akhir ini, telah dirancang dan diimplementasikan demapper 64-QAM yang merupakansub blok demodulator, pada FPGA (Field Programable Gate Array) yang menggunakan bahasa pengkodeanVery High Speed Integrated Cicuit (VHSIC) Hardware Description Language (VHDL) Fungsi dari blok iniadalah untuk memetakan balik simbol-simbol masukan dengan amplitudo dan fasa yang berbeda-beda yangsebelumnya telah direpresentasikan ke dalam bentuk bit-bit pada sisi pengirim. Pemetaan balik ini mengubahsimbol-simbol tersebut menjadi bit-bit informasi yang masih berupa bit-bit inphase dan quadrature.Dari hasil penelitian ini, untuk kondisi ideal atau gangguan didapatkan output di sisi penerima berupasebuah bit-bit informasi yang sama dengan bit-bit informasi yang dikirimkan pada sisi pengirim. Sedangkanuntuk kondisi ada gangguan, hasil outputnya masih sama dengan bit-bit informasi selama bit yang digangguadalah enam bit dari LSB (Least Significant bit), untuk tujuh bit yang diganggu error process yang terjadiadalah 21,8310 % sedangkan untuk empat belas bit yang diganggu error process yang terjadi sebesar 96,9072%.

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