Optimum Digital Filter for High-Performance All-Digital Phase-Locked Loop

2012 ◽  
Vol 182-183 ◽  
pp. 587-592
Author(s):  
Hua Fang Sun ◽  
Xin Ning Liu ◽  
Xin Chen
Keyword(s):  
Performance Improvement ◽  
Digital Filter ◽  
High Performance ◽  
Design Procedure ◽  
Phase Locked Loop ◽  
Timing Jitter ◽  
Systematic Design ◽  
Theoretic Analysis ◽  
Digital Phase ◽  
Significant Performance

The effect of all-digital phase-locked loop (ADPLL) digital filter parameters on the jitter is investigated in time domain, and a systematic design procedure for ADPLL is presented. The pro-posed method not only estimates the output jitter of an ADPLL, but also finds the optimal filter pa-rameter minimizing the overall ADPLL timing jitter. To verify the theoretic analysis, an ADPLL behavior model in matlab is designed. The simulation shows significant performance improvement on the timing jitter.

An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors

1995 ◽  
Vol 30 (4) ◽  
pp. 412-422 ◽  
Author(s):  
J. Dunning ◽  
G. Garcia ◽  
J. Lundberg ◽  
E. Nuckolls
Keyword(s):  
High Performance ◽  
Phase Locked Loop ◽  
Digital Phase

Sensorless Control Strategy for BLDC Motors Based on a Type-3 Phase Locked Loop

2021 ◽  
Author(s):  
Mohamed Abbes ◽  
Souad Chebbi
Keyword(s):  
Control Strategy ◽  
High Performance ◽  
Sensorless Control ◽  
Design Procedure ◽  
Phase Locked Loop ◽  
Control Technique ◽  
Loop Filter ◽  
Zero Crossing ◽  
Industrial Level ◽  
Type 3

This paper presents the design procedure of a high-performance sensorless control strategy for the widely used brushless DC (BLDC) motors. Generally, conventional sensorless techniques are based on detecting the zero-crossing instants (ZCP) of the back electromotives forces (back-EMFs) of the three phases. These methods, although widely adopted and marketed on an industrial level, involve many limitations such as filtering delays, difficulty to operate at low speeds and immunity against Electromagnetic Interferences (EMI). In this paper, the main objective is to develop a sensorless control technique integrally independent from the zero-crossing points of the back-EMFs. In the proposed method, a zero-delay adaptive filter was used to extract the fundamental and the quadrature components of the line-to-line voltage of the motor. Then, the Synchronous Reference Frame Phase Locked Loop (SRF-PLL) is used to estimate the electrical angle of phase-to-phase back-EMF along with the rotor speed. The conventional SRF-PLL was implemented using a second-order loop filter (type-3 PLL) in order to improve synchronization performances and for better rejection of voltage spikes induced in motor phases during commutations. The benefits of the control technique are brought to light through simulation results. An experimental prototype was designed to confirm the validity of the proposed method.

Performance Improvement of Digital Phase Locked Loop Algorithm Using all Pass Filter and Low Pass Filter for Grid Connected Inverter Reference

2013 ◽  
Vol 313-314 ◽  
pp. 1274-1278
Author(s):  
F. Yusivar ◽  
Y. Syaifuddin ◽  
A.N. Rahman
Keyword(s):  
Performance Improvement ◽  
Phase Locked Loop ◽  
High Accuracy ◽  
Reference Frequency ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Digital Phase ◽  
Low Pass ◽  
Grid Connected Inverter ◽  
Conventional Algorithm

Digital Phase Locked Loop (PLL) is an algorithm that is used to detect the phase, frequency, and amplitude of a signal. The output of digital PLL algorithm can be used as synchronization reference for grid connected inverter. A digital PLL algorithm is very popular to be used since its structure is very simple and it has high accuracy. However, the output of digital PLL is not stable if the input reference frequency is shifted from the pre-defined fundamental frequency and that condition will result an oscillation in digital PLL output. In this paper, an algorithm modification is employed using low pass filter and all pass filter to improve the digital PLL output response under various condition. All simulation results will be shown and compared to the conventional algorithm.

Epitaxially-crystallized oriented naphthalene bis(dicarboximide) morphology for significant performance improvement of electron-transporting thin-film transistors

2016 ◽  
Vol 52 (27) ◽  
pp. 4902-4905 ◽  
Author(s):  
Lili Liu ◽  
Zhongjie Ren ◽  
Chengyi Xiao ◽  
Bing He ◽  
Huanli Dong ◽  
...  
Keyword(s):  
Thin Film ◽  
Performance Improvement ◽  
Thin Film Transistors ◽  
High Performance ◽  
Large Area ◽  
Epitaxial Crystallization ◽  
Significant Performance

Large-area and well-ordered F-NDI films have been prepared for high performance OFETs by epitaxial crystallization on highly oriented PE substrates.

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