Design and Implementation of a Low-Cost Scalar Multiplier-on-Chip for Elliptic Curve Cryptosystem

2013 ◽  
Vol 284-287 ◽  
pp. 3395-3400
Author(s):  
Wen Tzeng Huang ◽  
Ching Kuo Wang ◽  
Guo Ming Sung ◽  
Chiu Ching Tuan
Keyword(s):  
Parallel Processing ◽  
Elliptic Curve ◽  
Circuit Design ◽  
Low Cost ◽  
Scalar Multiplication ◽  
Pipeline Architecture ◽  
And Performance ◽  
On Chip ◽  
Processor Cores ◽  
Processing Architecture

In the ECC, scalar multiplication represents the core operation of the system. In recent years, the circuit architecture of triple processor cores or greater has been addressed in the domestic and international literature. A parallel processing concept is mainly used in this type of framework to accelerate circuit operation. In the present study, equation calculation and circuit design were employed to integrate the pipeline architecture and the parallel processing architecture and further propose an elliptic curve scalar multiplier for dual processor cores. In addition, a Xilinx XC5VLX110T FPGA was used to verify the accuracy and performance of circuit functions. The maximum frequency was 173 MHz, the number of LUTs was 14999 slices, and the time to accomplishing one scalar multiplication was only 8.8s. Compared to architectures described in recent reports, the architecture presented was faster and effectively reduced the square measure by 28%.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

Parallelizing GF (p) Montgomery Elliptic Curve Crypto-System Operations to Improve Security and Performance

2012 ◽  
Vol 622-623 ◽  
pp. 1906-1911 ◽  
Author(s):  
Mohammad Alkhatib ◽  
Azmi Jaafar ◽  
Mohamad Rushdan Md Said ◽  
Zuriati Ahmad Zukarnain
Keyword(s):  
Time Delay ◽  
Elliptic Curve ◽  
Scalar Multiplication ◽  
Performance Level ◽  
Improve Performance ◽  
Homogeneous Coordinates ◽  
Simple Power ◽  
Lower Point ◽  
Hardware Implementations ◽  
And Performance

The elliptic curve crypto-system (ECC) performs two levels of computations, lower point operations, and upper scalar multiplication levels. The use of usual serial design and affine coordinates to apply ECC computations increases the time delay and weaken the security of the crypto-system against simple power attack (SPA). This work combines the inherited parallelism in both computation levels for GF (p) Montgomery ECC to improve performance and enhance the immunity of the ECC against SPA. Moreover, projective coordinates were used to apply ECC operations to eliminate the time-consuming inversion operation. In order to increase the speed even further, this paper proposes to use known NAF algorithm for scalar multiplication, as well as Montgomery multiplier to perform multiplication operations. Hardware implementations with target FPGA for GF (p) Montgomery ECC are also presented. The best performance level was achieved when parallelizing Montgomery ECC computations to eight parallel multipliers (PM) using homogeneous coordinates. Such strategy, although it requires extra resources, is worth considering due to its attractive security and performance conclusions.

Design of Advanced High Performance Bus Tracer in System on Chip Using Matrix Based Compression for Low Power Applications

2020 ◽  
Vol 17 (4) ◽  
pp. 1852-1856
Author(s):  
P. Bhuvaneshwari ◽  
T. R. Jaya Chandra Lekha
Keyword(s):  
Low Power ◽  
High Performance ◽  
Performance Monitoring ◽  
Low Cost ◽  
System On Chip ◽  
Consumer Electronics ◽  
Compression Scheme ◽  
Control Signals ◽  
And Performance ◽  
On Chip

This project proposes multilayer advanced high-performance bus architecture for low power applications. The proposed AHB architecture consists of the bus arbiter and the bus tracer (A.R.M.A., 1999. Specification (Rev 2.0) ARM IHI0011A). The bus arbiter, which is self motivated selects the input packet based on the control signals of the incoming packet. So that arbitration leads to a maximum performance. The On-Chip bus is an important system-on-chip infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization (Gu, R.T., et al., 2007. A Low Cost Tile-Based 3D Graphics Full Pipeline with Real-Time Performance Monitoring Support for OpenGL ES in Consumer Electronics. 2007 IEEE International Symposium on Consumer Electronics, June; IEEE. pp.1–6). But, such signals are difficult to observe since they are deeply embedded in a SoC and there are often no sufficient I/O pins to access these signals. Therefore, a straightforward approach is to embed a bus tracer in SoC to capture the bus signal trace and store the trace in on-chip storage such as the trace memory which could then be off loaded to outside world for analysis. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built in compression mechanisms such as dictionary based compression scheme for address and control signals and differential compression scheme for data. To improve the compression ratio matrix based compression which is lossless compression is used instead of differential compression. This system is designed using Verilog HDL, simulated using Modelsim and synthesized using Xilinx software.

scholarly journals Internet of things-based photovoltaics parameter monitoring system using NodeMCU ESP8266

2021 ◽  
Vol 11 (6) ◽  
pp. 5578
Author(s):  
Tole Sutikno ◽  
Hendril Satrian Purnama ◽  
Anggit Pamungkas ◽  
Abdul Fadlil ◽  
Ibrahim Mohd Alsofyani ◽  
...  
Keyword(s):  
Internet Of Things ◽  
Monitoring System ◽  
Low Cost ◽  
Critical Feature ◽  
Pv Systems ◽  
Network Connection ◽  
Use Of The Internet ◽  
And Performance ◽  
On Chip ◽  
Parameter Monitoring

<span>The use of the internet of things (IoT) in solar photovoltaic (PV) systems is a critical feature for remote monitoring, supervising, and performance evaluation. Furthermore, it improves the long-term viability, consistency, efficiency, and system maintenance of energy production. However, previous researchers' proposed PV monitoring systems are relatively complex and expensive. Furthermore, the existing systems do not have any backup data, which means that the acquired data could be lost if the network connection fails. This paper presents a simple and low-cost IoT-based PV parameter monitoring system, with additional backup data stored on a microSD card. A NodeMCU ESP8266 development board is chosen as the main controller because it is a system-on-chip (SOC) microcontroller with integrated Wi-Fi and low-power support, all in one chip to reduce the cost of the proposed system. The solar irradiance, ambient temperature, PV output voltage and PV output current, are measured with photo-diodes, DHT22, impedance dividers and ACS712. While, the PV output power is a product of the PV voltage and PV current. ThingSpeak, an open-source software, is used as a cloud database and data monitoring tool in the form of interactive graphics. The results showed that the system was designed to be highly accurate, reliable, simple to use, and low-cost.</span>

scholarly journals Multiprotocol Authentication Device for HPC and Cloud Environments Based on Elliptic Curve Cryptography

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1148
Author(s):  
Antonio F. Díaz ◽  
Ilia Blokhin ◽  
Mancia Anguita ◽  
Julio Ortega ◽  
Juan J. Escobar
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
High Performance ◽  
Low Cost ◽  
System On Chip ◽  
Access To Services ◽  
Multifactor Authentication ◽  
Server Systems ◽  
On Chip ◽  
The Impact

Multifactor authentication is a relevant tool in securing IT infrastructures combining two or more credentials. We can find smartcards and hardware tokens to leverage the authentication process, but they have some limitations. Users connect these devices in the client node to log in or request access to services. Alternatively, if an application wants to use these resources, the code has to be amended with bespoke solutions to provide access. Thanks to advances in system-on-chip devices, we can integrate cryptographically robust, low-cost solutions. In this work, we present an autonomous device that allows multifactor authentication in client–server systems in a transparent way, which facilitates its integration in High-Performance Computing (HPC) and cloud systems, through a generic gateway. The proposed electronic token (eToken), based on the system-on-chip ESP32, provides an extra layer of security based on elliptic curve cryptography. Secure communications between elements use Message Queuing Telemetry Transport (MQTT) to facilitate their interconnection. We have evaluated different types of possible attacks and the impact on communications. The proposed system offers an efficient solution to increase security in access to services and systems.

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