Efficient Graph Component Labeling on Hybrid CPU and GPU Platforms

2014 ◽  
Vol 596 ◽  
pp. 276-279
Author(s):  
Xiao Hui Pan
Keyword(s):  
High Performance ◽  
General Purpose ◽  
Gpu Programming ◽  
Data Parallel ◽  
Graphical Processing Units ◽  
Architectural Features ◽  
Graph Coloring Problem ◽  
Graphical Processing ◽  
And Performance ◽  
Performance Results

Graph component labeling, which is a subset of the general graph coloring problem, is a computationally expensive operation in many important applications and simulations. A number of data-parallel algorithmic variations to the component labeling problem are possible and we explore their use with general purpose graphical processing units (GPGPUs) and with the CUDA GPU programming language. We discuss implementation issues and performance results on CPUs and GPUs using CUDA. We evaluated our system with real-world graphs. We show how to consider different architectural features of the GPU and the host CPUs and achieve high performance.

scholarly journals RUMD: A general purpose molecular dynamics package optimized to utilize GPU hardware down to a few thousand particles

2017 ◽  
Vol 3 (6) ◽  
Author(s):  
Nicholas Bailey ◽  
Trond Ingebrigtsen ◽  
Jesper Schmidt Hansen ◽  
Arno Veldhorst ◽  
Lasse Bøhling ◽  
...  
Keyword(s):  
Molecular Dynamics ◽  
High Performance ◽  
General Purpose ◽  
Graphical Processing Units ◽  
Performance Benchmarks ◽  
Graphical Processing ◽  
And Performance ◽  
Set Up ◽  
The Many ◽  
Many Core

RUMD is a general purpose, high-performance molecular dynamics (MD) simulation package running on graphical processing units (GPU’s). RUMD addresses the challenge of utilizing the many-core nature of modern GPU hardware when simulating small to medium system sizes (roughly from a few thousand up to hundred thousand particles). It has a performance that is comparable to other GPU-MD codes at large system sizes and substantially better at smaller sizes. RUMD is open-source and consists of a library written in C++ and the CUDA extension to C, an easy-to-use Python interface, and a set of tools for set-up and post-simulation data analysis. The paper describes RUMD’s main features, optimizations and performance benchmarks.

scholarly journals Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory

2014 ◽  
Vol 22 (2) ◽  
pp. 125-139 ◽  
Author(s):  
Myoungsoo Jung ◽  
Ellis H. Wilson ◽  
Wonil Choi ◽  
John Shalf ◽  
Hasan Metin Aktulga ◽  
...  
Keyword(s):  
High Performance ◽  
File Systems ◽  
Network Capacity ◽  
General Purpose ◽  
Graphical Processing Units ◽  
Non Volatile Memory ◽  
Order Of Magnitude ◽  
Volatile Memory ◽  
Graphical Processing ◽  
Point To Point

Drawing parallels to the rise of general purpose graphical processing units (GPGPUs) as accelerators for specific high-performance computing (HPC) workloads, there is a rise in the use of non-volatile memory (NVM) as accelerators for I/O-intensive scientific applications. However, existing works have explored use of NVM within dedicated I/O nodes, which are distant from the compute nodes that actually need such acceleration. As NVM bandwidth begins to out-pace point-to-point network capacity, we argue for the need to break from the archetype of completely separated storage. Therefore, in this work we investigate co-location of NVM and compute by varying I/O interfaces, file systems, types of NVM, and both current and future SSD architectures, uncovering numerous bottlenecks implicit in these various levels in the I/O stack. We present novel hardware and software solutions, including the new Unified File System (UFS), to enable fuller utilization of the new compute-local NVM storage. Our experimental evaluation, which employs a real-world Out-of-Core (OoC) HPC application, demonstrates throughput increases in excess of an order of magnitude over current approaches.

scholarly journals Run-Time and Compiler Support for Programming in Adaptive Parallel Environments

1997 ◽  
Vol 6 (2) ◽  
pp. 215-227 ◽  
Author(s):  
Guy Edjlali ◽  
Gagan Guyagrawal ◽  
Alan Sussman ◽  
Jim Humphries ◽  
Joel Saltz
Keyword(s):  
Parallel Programming ◽  
High Performance ◽  
Navier Stokes ◽  
Programming Environments ◽  
Data Parallel ◽  
Adaptive Environment ◽  
Run Time ◽  
Time Required ◽  
The Cost ◽  
Performance Results

For better utilization of computing resources, it is important to consider parallel programming environments in which the number of available processors varies at run-time. In this article, we discuss run-time support for data-parallel programming in such an adaptive environment. Executing programs in an adaptive environment requires redistributing data when the number of processors changes, and also requires determining new loop bounds and communication patterns for the new set of processors. We have developed a run-time library to provide this support. We discuss how the run-time library can be used by compilers of high-performance Fortran (HPF)-like languages to generate code for an adaptive environment. We present performance results for a Navier-Stokes solver and a multigrid template run on a network of workstations and an IBM SP-2. Our experiments show that if the number of processors is not varied frequently, the cost of data redistribution is not significant compared to the time required for the actual computation. Overall, our work establishes the feasibility of compiling HPF for a network of nondedicated workstations, which are likely to be an important resource for parallel programming in the future.

scholarly journals A SCALABLE DISTRIBUTED MULTIMEDIA KNOWLEDGE RETRIEVAL SYSTEM ON A CLUSTER OF HETEROGENEOUS HIGH PERFORMANCE ARCHITECTURES

2000 ◽  
Vol 09 (03) ◽  
pp. 343-367
Author(s):  
STEPHEN W. RYAN ◽  
ARVIND K. BANSAL
Keyword(s):  
Logic Programming ◽  
Message Passing ◽  
High Performance ◽  
Programming Model ◽  
Object Oriented Programming ◽  
Remote Access ◽  
The Internet ◽  
Data Parallel ◽  
Heterogeneous Architectures ◽  
Performance Results

This paper describes a system to distribute and retrieve multimedia knowledge on a cluster of heterogeneous high performance architectures distributed over the Internet. The knowledge is represented using facts and rules in an associative logic-programming model. Associative computation facilitates distribution of facts and rules, and exploits coarse grain data parallel computation. Associative logic programming uses a flat data model that can be easily mapped onto heterogeneous architectures. The paper describes an abstract instruction set for the distributed version of the associative logic programming and the corresponding implementation. The implementation uses a message-passing library for architecture independence within a cluster, uses object oriented programming for modularity and portability, and uses Java as a front-end interface to provide a graphical user interface and multimedia capability and remote access via the Internet. The performance results on a cluster of IBM RS 6000 workstations are presented. The results show that distribution of data improves the performance almost linearly for small number of processors in a cluster.

scholarly journals Accelerated FDPS: Algorithms to use accelerators with FDPS

2020 ◽  
Vol 72 (1) ◽  
Author(s):  
Masaki Iwasawa ◽  
Daisuke Namekata ◽  
Keigo Nitadori ◽  
Kentaro Nomura ◽  
Long Wang ◽  
...  
Keyword(s):  
Graphics Processing Units ◽  
High Performance ◽  
General Purpose ◽  
Performance Model ◽  
Performance Tuning ◽  
Data Types ◽  
Interaction Function ◽  
Current Implementation ◽  
And Performance ◽  
Graphics Processing

Abstract We describe algorithms implemented in FDPS (Framework for Developing Particle Simulators) to make efficient use of accelerator hardware such as GPGPUs (general-purpose computing on graphics processing units). We have developed FDPS to make it possible for researchers to develop their own high-performance parallel particle-based simulation programs without spending large amounts of time on parallelization and performance tuning. FDPS provides a high-performance implementation of parallel algorithms for particle-based simulations in a “generic” form, so that researchers can define their own particle data structure and interparticle interaction functions. FDPS compiled with user-supplied data types and interaction functions provides all the necessary functions for parallelization, and researchers can thus write their programs as though they are writing simple non-parallel code. It has previously been possible to use accelerators with FDPS by writing an interaction function that uses the accelerator. However, the efficiency was limited by the latency and bandwidth of communication between the CPU and the accelerator, and also by the mismatch between the available degree of parallelism of the interaction function and that of the hardware parallelism. We have modified the interface of the user-provided interaction functions so that accelerators are more efficiently used. We also implemented new techniques which reduce the amount of work on the CPU side and the amount of communication between CPU and accelerators. We have measured the performance of N-body simulations on a system with an NVIDIA Volta GPGPU using FDPS and the achieved performance is around 27% of the theoretical peak limit. We have constructed a detailed performance model, and found that the current implementation can achieve good performance on systems with much smaller memory and communication bandwidth. Thus, our implementation will be applicable to future generations of accelerator system.

scholarly journals AN ASSOCIATIVE DATA PARALLEL COMPILATION MODEL FOR TIGHT INTEGRATION OF HIGH PERFORMANCE KNOWLEDGE RETRIEVAL AND COMPUTING

1994 ◽  
Vol 03 (01) ◽  
pp. 97-125 ◽  
Author(s):  
ARVIND K. BANSAL
Keyword(s):  
Performance Evaluation ◽  
High Performance ◽  
Loose Coupling ◽  
Abstract Machine ◽  
Data Movement ◽  
Left Hand ◽  
Low Level ◽  
Data Parallel ◽  
Data Alignment ◽  
And Performance

Associative Computation is characterized by intertwining of search by content and data parallel computation. An algebra for associative computation is described. A compilation based model and a novel abstract machine for associative logic programming are presented. The model uses loose coupling of left hand side of the program, treated as data, and right hand side of the program, treated as low level code. This representation achieves efficiency by associative computation and data alignment during goal reduction and during execution of low level abstract instructions. Data alignment reduces the overhead of data movement. Novel schemes for associative manipulation of aliased uninstantiated variables, data parallel goal reduction in the presence multiple occurrences of the same variables in a goal. The architecture, behavior, and performance evaluation of the model are presented.

SIMinG-1k: A thousand-core simulator running on general-purpose graphical processing units

2012 ◽  
Vol 25 (10) ◽  
pp. 1443-1461 ◽  
Author(s):  
Shivani Raghav ◽  
Andrea Marongiu ◽  
Christian Pinto ◽  
Martino Ruggiero ◽  
David Atienza ◽  
...  
Keyword(s):  
General Purpose ◽  
Graphical Processing Units ◽  
Graphical Processing

A FRAMEWORK FOR HETEROGENEOUS ASSOCIATIVE LOGIC PROGRAMMING

1995 ◽  
Vol 04 (01n02) ◽  
pp. 33-53 ◽  
Author(s):  
ARVIND K. BANSAL
Keyword(s):  
Logic Programming ◽  
High Performance ◽  
Heterogeneous Computing ◽  
Data Transfer ◽  
Instruction Set ◽  
Data Parallel ◽  
Data Alignment ◽  
Resolution Scheme ◽  
Data Elements ◽  
Performance Results

Associative computation is characterized by seamless intertwining of search-by-content and data parallel computation. The search-by-content paradigm is natural to scalable high performance heterogeneous computing since the use of tagged data avoids the need for explicit addressing mechanisms. In this paper, the author presents an algebra for associative logic programming, an associative resolution scheme, and a generic framework of an associative abstract instruction set. The model is based on the integration of data alignment and the use of two types of bags: data element bags and filter bags of Boolean values to select and restrict computation on data elements. The use of filter bags integrated with data alignment reduces computation and data transfer overhead, and the use of tagged data reduces overhead of preparing data before data transmission. The abstract instruction set has been illustrated by an example. Performance results are presented for a simulation in a homogeneous address space.

High-Performance Computing for Theoretical Study of Nanoscale and Molecular Interconnects

2014 ◽  
pp. 513-532
Author(s):  
Rasit O. Topaloglu ◽  
Swati R. Manjari ◽  
Saroj K. Nayak
Keyword(s):  
Integrated Circuits ◽  
High Performance Computing ◽  
Real World ◽  
High Performance ◽  
Quantum Effects ◽  
Accurate Analysis ◽  
Graphical Processing Units ◽  
Graphical Processing ◽  
Silicon Based ◽  
Performance Computing

Interconnects in semiconductor integrated circuits have shrunk to nanoscale sizes. This size reduction requires accurate analysis of the quantum effects. Furthermore, improved low-resistance interconnects need to be discovered that can integrate with biological and nanoelectronic systems. Accurate system-scale simulation of these quantum effects is possible with high-performance computing (HPC), while high cost and poor feasibility of experiments also suggest the application of simulation and HPC. This chapter introduces computational nanoelectronics, presenting real-world applications for the simulation and analysis of nanoscale and molecular interconnects, which may provide the connection between molecules and silicon-based devices. We survey computational nanoelectronics of interconnects and analyze four real-world case studies: 1) using graphical processing units (GPUs) for nanoelectronic simulations; 2) HPC simulations of current flow in nanotubes; 3) resistance analysis of molecular interconnects; and 4) electron transport improvement in graphene interconnects. In conclusion, HPC simulations are promising vehicles to advance interconnects and study their interactions with molecular/biological structures in support of traditional experimentation.

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